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Searched refs:pll_base (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/clk/imx/
H A Dclk-imxrt1050.c39 void __iomem *pll_base; in imxrt1050_clocks_probe() local
56 pll_base = devm_of_iomap(dev, anp, 0, NULL); in imxrt1050_clocks_probe()
58 if (WARN_ON(IS_ERR(pll_base))) { in imxrt1050_clocks_probe()
59 ret = PTR_ERR(pll_base); in imxrt1050_clocks_probe()
67 pll_base + 0x0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imxrt1050_clocks_probe()
69 pll_base + 0x30, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imxrt1050_clocks_probe()
71 pll_base + 0x10, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imxrt1050_clocks_probe()
73 pll_base + 0xa0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imxrt1050_clocks_probe()
76 "pll1_arm_ref_sel", pll_base + 0x0, 0x7f); in imxrt1050_clocks_probe()
78 "pll2_sys_ref_sel", pll_base + 0x30, 0x1); in imxrt1050_clocks_probe()
[all …]
H A Dclk-imx5.c283 void __iomem *pll_base; in mx50_clocks_init() local
286 pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K); in mx50_clocks_init()
287 WARN_ON(!pll_base); in mx50_clocks_init()
288 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); in mx50_clocks_init()
290 pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K); in mx50_clocks_init()
291 WARN_ON(!pll_base); in mx50_clocks_init()
292 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); in mx50_clocks_init()
294 pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K); in mx50_clocks_init()
295 WARN_ON(!pll_base); in mx50_clocks_init()
296 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); in mx50_clocks_init()
[all …]
/linux/drivers/clk/visconti/
H A Dpll.c21 void __iomem *pll_base; member
61 val = readl(pll->pll_base + PLL_FRACMODE_REG); in visconti_pll_get_params()
66 rate_table->fracin = readl(pll->pll_base + PLL_FRACIN_REG) & PLL_FRACIN_MASK; in visconti_pll_get_params()
67 rate_table->intin = readl(pll->pll_base + PLL_INTIN_REG) & PLL_INTIN_MASK; in visconti_pll_get_params()
68 rate_table->refdiv = readl(pll->pll_base + PLL_REFDIV_REG) & PLL_REFDIV_MASK; in visconti_pll_get_params()
70 postdiv = readl(pll->pll_base + PLL_POSTDIV_REG); in visconti_pll_get_params()
134 writel(PLL_CREATE_FRACMODE(rate_table), pll->pll_base + PLL_FRACMODE_REG); in visconti_pll_set_params()
135 writel(PLL_CREATE_OSTDIV(rate_table), pll->pll_base + PLL_POSTDIV_REG); in visconti_pll_set_params()
136 writel(rate_table->intin, pll->pll_base + PLL_INTIN_REG); in visconti_pll_set_params()
137 writel(rate_table->fracin, pll->pll_base + PLL_FRACIN_REG); in visconti_pll_set_params()
[all …]
/linux/arch/mips/ath79/
H A Dclock.c93 static void __init ar71xx_clocks_init(void __iomem *pll_base) in ar71xx_clocks_init() argument
105 pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
124 static void __init ar724x_clocks_init(void __iomem *pll_base) in ar724x_clocks_init() argument
131 pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); in ar724x_clocks_init()
144 static void __init ar933x_clocks_init(void __iomem *pll_base) in ar933x_clocks_init() argument
165 clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG); in ar933x_clocks_init()
178 cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG); in ar933x_clocks_init()
232 static void __init ar934x_clocks_init(void __iomem *pll_base) in ar934x_clocks_init() argument
265 pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG); in ar934x_clocks_init()
292 pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG); in ar934x_clocks_init()
[all …]
/linux/drivers/clk/microchip/
H A Dclk-mpfs-ccc.c37 void __iomem **pll_base; member
173 out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] + in mpfs_ccc_register_outputs()
209 pll_hw->base = data->pll_base[i]; in mpfs_ccc_register_plls()
233 void __iomem *pll_base[ARRAY_SIZE(mpfs_ccc_pll_clks)]; in mpfs_ccc_probe() local
245 pll_base[0] = devm_platform_ioremap_resource(pdev, 0); in mpfs_ccc_probe()
246 if (IS_ERR(pll_base[0])) in mpfs_ccc_probe()
247 return PTR_ERR(pll_base[0]); in mpfs_ccc_probe()
249 pll_base[1] = devm_platform_ioremap_resource(pdev, 1); in mpfs_ccc_probe()
250 if (IS_ERR(pll_base[1])) in mpfs_ccc_probe()
251 return PTR_ERR(pll_base[1]); in mpfs_ccc_probe()
[all …]
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dvideo-pll.c133 void __iomem *pll_base, *clkctrl_base; in dss_video_pll_init() local
140 pll_base = devm_platform_ioremap_resource_byname(pdev, reg_name[id]); in dss_video_pll_init()
141 if (IS_ERR(pll_base)) { in dss_video_pll_init()
143 return ERR_CAST(pll_base); in dss_video_pll_init()
175 pll->base = pll_base; in dss_video_pll_init()
H A Ddsi.c295 void __iomem *pll_base; member
441 case DSI_PLL: base = dsi->pll_base; break; in dsi_write_reg()
457 case DSI_PLL: base = dsi->pll_base; break; in dsi_read_reg()
5225 pll->base = dsi->pll_base; in dsi_init_pll_data()
5350 dsi->pll_base = devm_ioremap(&dsidev->dev, res->start, in dsi_bind()
5352 if (!dsi->pll_base) { in dsi_bind()
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dvideo-pll.c141 void __iomem *pll_base, *clkctrl_base; in dss_video_pll_init() local
148 pll_base = devm_platform_ioremap_resource_byname(pdev, reg_name[id]); in dss_video_pll_init()
149 if (IS_ERR(pll_base)) in dss_video_pll_init()
150 return ERR_CAST(pll_base); in dss_video_pll_init()
179 pll->base = pll_base; in dss_video_pll_init()
H A Ddsi.h343 void __iomem *pll_base; member
H A Ddsi.c94 case DSI_PLL: base = dsi->pll_base; break; in dsi_write_reg()
108 case DSI_PLL: base = dsi->pll_base; break; in dsi_read_reg()
4543 pll->base = dsi->pll_base; in dsi_init_pll_data()
4933 dsi->pll_base = devm_platform_ioremap_resource_byname(pdev, "pll"); in dsi_probe()
4934 if (IS_ERR(dsi->pll_base)) in dsi_probe()
4935 return PTR_ERR(dsi->pll_base); in dsi_probe()
/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_28nm_8960.c77 val = readl(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_RDY); in pll_28nm_poll_for_ready()
97 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_clk_set_rate()
141 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_clk_recalc_rate()
175 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_vco_prepare()
228 writel(0x00, pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0); in dsi_pll_28nm_vco_unprepare()
342 void __iomem *base = pll_28nm->phy->pll_base; in dsi_28nm_pll_save_state()
358 void __iomem *base = pll_28nm->phy->pll_base; in dsi_28nm_pll_restore_state()
410 bytediv->reg = pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9; in pll_28nm_register()
431 &pll_28nm->clk_hw, 0, pll_28nm->phy->pll_base + in pll_28nm_register()
H A Ddsi_phy_28nm.c86 val = readl(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_STATUS); in pll_28nm_poll_for_ready()
101 void __iomem *base = pll_28nm->phy->pll_base; in pll_28nm_software_reset()
121 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_clk_set_rate()
245 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_clk_recalc_rate()
292 void __iomem *base = pll_28nm->phy->pll_base; in _dsi_pll_28nm_vco_prepare_hpm()
396 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_vco_prepare_8226()
470 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_vco_prepare_lp()
530 writel(0, pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_GLB_CFG); in dsi_pll_28nm_vco_unprepare()
583 void __iomem *base = pll_28nm->phy->pll_base; in dsi_28nm_pll_save_state()
600 void __iomem *base = pll_28nm->phy->pll_base; in dsi_28nm_pll_restore_state()
[all …]
H A Ddsi_phy_10nm.c185 void __iomem *base = pll->phy->pll_base; in dsi_pll_ssc_commit()
209 void __iomem *base = pll->phy->pll_base; in dsi_pll_config_hzindep_reg()
233 void __iomem *base = pll->phy->pll_base; in dsi_pll_commit()
287 rc = readl_poll_timeout_atomic(pll->phy->pll_base + in dsi_pll_10nm_lock_status()
304 writel(0, pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES); in dsi_pll_disable_pll_bias()
314 writel(0xc0, pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES); in dsi_pll_enable_pll_bias()
411 void __iomem *base = pll_10nm->phy->pll_base; in dsi_pll_10nm_vco_recalc_rate()
478 cached->pll_out_div = readl(pll_10nm->phy->pll_base + in dsi_10nm_pll_save_state()
502 val = readl(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); in dsi_10nm_pll_restore_state()
505 writel(val, pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); in dsi_10nm_pll_restore_state()
[all …]
H A Ddsi_phy_7nm.c202 void __iomem *base = pll->phy->pll_base; in dsi_pll_ssc_commit()
226 void __iomem *base = pll->phy->pll_base; in dsi_pll_config_hzindep_reg()
283 writel(0x22, pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE); in dsi_pll_config_hzindep_reg()
289 void __iomem *base = pll->phy->pll_base; in dsi_pll_commit()
344 rc = readl_poll_timeout_atomic(pll->phy->pll_base + in dsi_pll_7nm_lock_status()
361 writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES); in dsi_pll_disable_pll_bias()
371 writel(0xc0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES); in dsi_pll_enable_pll_bias()
481 void __iomem *base = pll_7nm->phy->pll_base; in dsi_pll_7nm_vco_recalc_rate()
548 cached->pll_out_div = readl(pll_7nm->phy->pll_base + in dsi_7nm_pll_save_state()
572 val = readl(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); in dsi_7nm_pll_restore_state()
[all …]
H A Ddsi_phy_14nm.c114 void __iomem *base = pll_14nm->phy->pll_base; in pll_14nm_poll_for_ready()
286 void __iomem *base = pll->phy->pll_base; in pll_db_commit_ssc()
321 void __iomem *base = pll->phy->pll_base; in pll_db_commit_common()
388 void __iomem *base = pll->phy->pll_base; in pll_db_commit_14nm()
497 void __iomem *base = pll_14nm->phy->pll_base; in dsi_pll_14nm_vco_recalc_rate()
536 void __iomem *base = pll_14nm->phy->pll_base; in dsi_pll_14nm_vco_prepare()
745 void __iomem *base = phy->pll_base; in dsi_14nm_set_usecase()
H A Ddsi_phy.h95 void __iomem *pll_base; member
H A Ddsi_phy.c662 phy->pll_base = msm_ioremap_size(pdev, "dsi_pll", &phy->pll_size); in dsi_phy_driver_probe()
663 if (IS_ERR(phy->pll_base)) in dsi_phy_driver_probe()
664 return dev_err_probe(dev, PTR_ERR(phy->pll_base), in dsi_phy_driver_probe()
869 phy->pll_size, phy->pll_base, in msm_dsi_phy_snapshot()
/linux/drivers/clk/
H A Dclk-sp7021.c588 #define PLLA_CTL (pll_base + 0x1c)
589 #define PLLE_CTL (pll_base + 0x30)
590 #define PLLF_CTL (pll_base + 0x34)
591 #define PLLTV_CTL (pll_base + 0x38)
601 void __iomem *clk_base, *pll_base, *sys_base; in sp7021_clk_probe() local
609 pll_base = devm_platform_ioremap_resource(pdev, 1); in sp7021_clk_probe()
610 if (IS_ERR(pll_base)) in sp7021_clk_probe()
611 return PTR_ERR(pll_base); in sp7021_clk_probe()
H A Dclk-bm1880.c63 void __iomem *pll_base; member
530 void __iomem *pll_base = data->pll_base; in bm1880_clk_register_plls() local
536 hw = bm1880_clk_register_pll(bm1880_clk, pll_base); in bm1880_clk_register_plls()
877 void __iomem *pll_base, *sys_base; in bm1880_clk_probe() local
881 pll_base = devm_platform_ioremap_resource(pdev, 0); in bm1880_clk_probe()
882 if (IS_ERR(pll_base)) in bm1880_clk_probe()
883 return PTR_ERR(pll_base); in bm1880_clk_probe()
900 clk_data->pll_base = pll_base; in bm1880_clk_probe()
/linux/arch/arm/mach-tegra/
H A Dsleep-tegra20.S57 .macro store_pll_state, rd, tmp, r_car_base, pll_base, pll_mask
58 ldr \rd, [\r_car_base, #\pll_base]
67 .macro pll_enable, rd, r_car_base, pll_base, test_mask
71 ldr \rd, [\r_car_base, #\pll_base]
74 streq \rd, [\r_car_base, #\pll_base]
H A Dsleep-tegra30.S104 .macro store_pll_state, rd, tmp, r_car_base, pll_base, pll_mask
105 ldr \rd, [\r_car_base, #\pll_base]
132 .macro pll_enable, rd, r_car_base, pll_base, pll_misc, test_mask
136 ldr \rd, [\r_car_base, #\pll_base]
139 streq \rd, [\r_car_base, #\pll_base]
153 .macro pll_locked, rd, r_car_base, pll_base, test_mask
157 ldr \rd, [\r_car_base, #\pll_base]
/linux/drivers/clk/st/
H A Dclkgen-pll.c755 void __iomem *pll_base; in clkgen_c32_pll_setup() local
765 pll_base = clkgen_get_register_base(np); in clkgen_c32_pll_setup()
766 if (!pll_base) in clkgen_c32_pll_setup()
771 clk = clkgen_pll_register(parent_name, datac->data, pll_base, pll_flags, in clkgen_c32_pll_setup()
808 clk = clkgen_odf_register(pll_name, pll_base, datac->data, in clkgen_c32_pll_setup()