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Searched refs:pll3 (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/clk/sunxi/
H A DMakefile18 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun4i-pll3.o
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h209 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
H A Dintel_dpll_mgr.c2085 PORT_PLL_M2_FRAC_ENABLE, hw_state->pll3); in bxt_ddi_pll_enable()
2201 hw_state->pll3 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 3)); in bxt_ddi_pll_get_hw_state()
2202 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_pll_get_hw_state()
2341 hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_set_dpll_hw_state()
2370 if (hw_state->pll3 & PORT_PLL_M2_FRAC_ENABLE) in bxt_ddi_pll_get_freq()
2465 hw_state->pll0, hw_state->pll1, hw_state->pll2, hw_state->pll3, in bxt_dump_hw_state()
2481 a->pll3 == b->pll3 && in bxt_compare_hw_state()
/linux/drivers/gpu/drm/tegra/
H A Dsor.c370 unsigned int pll3; member
2291 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2293 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2511 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2520 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2774 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2776 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_dp_enable()
3287 .pll3 = 0x1a,
3459 .pll3 = 0x1a,
3520 .pll3 = 0x166,
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/linux/drivers/clk/qcom/
H A Dgcc-ipq806x.c61 static struct clk_pll pll3 = { variable
324 { .hw = &pll3.clkr.hw },
385 { .hw = &pll3.clkr.hw },
3069 [PLL3] = &pll3.clkr,
H A Dgcc-msm8960.c29 static struct clk_pll pll3 = { variable
328 { .hw = &pll3.clkr.hw },
3243 [PLL3] = &pll3.clkr,
3471 [PLL3] = &pll3.clkr,
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8064.dtsi742 "pll3",