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Searched refs:pll2 (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/mfd/
H A Dsm501.c116 static unsigned long decode_div(unsigned long pll2, unsigned long val, in decode_div() argument
121 pll2 = 288 * MHZ; in decode_div()
123 return pll2 / div_tab[(val >> lshft) & mask]; in decode_div()
140 unsigned long pll2 = 0; in sm501_dump_clk() local
144 pll2 = 336 * MHZ; in sm501_dump_clk()
147 pll2 = 288 * MHZ; in sm501_dump_clk()
150 pll2 = 240 * MHZ; in sm501_dump_clk()
153 pll2 = 192 * MHZ; in sm501_dump_clk()
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c208 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; in setPLL_double_highregs() local
218 pll2 = 0; in setPLL_double_highregs()
227 pll2 |= 0x011f; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
266 nvkm_wr32(device, reg2, pll2); in setPLL_double_highregs()
/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c133 uint32_t pll2, struct nvkm_pll_vals *pllvals) in nouveau_hw_decode_pll() argument
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
151 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
193 pll2 = 0; in nouveau_hw_get_pllvals()
196 pll2 = 0; in nouveau_hw_get_pllvals()
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/linux/drivers/media/i2c/
H A Dov7251.c108 const struct ov7251_pll2_cfg *pll2; member
217 .pll2 = &ov7251_pll2_cfg_19_2_mhz,
225 .pll2 = &ov7251_pll2_cfg_24_mhz,
839 configs->pll2->pre_div); in ov7251_pll_configure()
844 configs->pll2->mult); in ov7251_pll_configure()
849 configs->pll2->div); in ov7251_pll_configure()
854 configs->pll2->sys_div); in ov7251_pll_configure()
859 configs->pll2->adc_div); in ov7251_pll_configure()
/linux/drivers/gpu/drm/tegra/
H A Dsor.c371 unsigned int pll2; member
1457 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1459 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1467 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1470 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
2289 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2291 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2304 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2306 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2310 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
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/linux/drivers/clk/mxs/
H A Dclk-imx28.c133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
/linux/drivers/clk/sunxi/
H A DMakefile12 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-pll2.o
/linux/drivers/clk/spacemit/
H A Dccu-k3.c150 CCU_PLLA_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR2, APBS_PLL2_SWCR3,
178 CCU_FACTOR_GATE_DEFINE(pll2_d1, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(0), 1, 1);
179 CCU_FACTOR_GATE_DEFINE(pll2_d2, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(1), 2, 1);
180 CCU_FACTOR_GATE_DEFINE(pll2_d3, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(2), 3, 1);
181 CCU_FACTOR_GATE_DEFINE(pll2_d4, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(3), 4, 1);
182 CCU_FACTOR_GATE_DEFINE(pll2_d5, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(4), 5, 1);
183 CCU_FACTOR_GATE_DEFINE(pll2_d6, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(5), 6, 1);
184 CCU_FACTOR_GATE_DEFINE(pll2_d7, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(6), 7, 1);
185 CCU_FACTOR_GATE_DEFINE(pll2_d8, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(7), 8, 1);
1138 [CLK_PLL2] = &pll2
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/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi242 pll2: pll2@0 { label
253 clocks = <&pll2>;
268 clocks = <&pll2>;
276 clocks = <&pll2>;
/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,dra7-dss.txt24 'pll1', 'pll2_clkctrl', 'pll2'
/linux/drivers/clk/
H A Dclk-k230.c275 K230_CLK_PLL_FORMAT(pll2, 2, CLK_IS_CRITICAL, NULL);
281 &pll2,
292 K230_CLK_FIXED_FACTOR_FORMAT(pll2_div2, 1, 2, 0, &pll2.hw);
293 K230_CLK_FIXED_FACTOR_FORMAT(pll2_div3, 1, 3, 0, &pll2.hw);
294 K230_CLK_FIXED_FACTOR_FORMAT(pll2_div4, 1, 4, 0, &pll2.hw);
/linux/drivers/clk/qcom/
H A Dmmcc-msm8960.c42 static struct clk_pll pll2 = { variable
101 { .hw = &pll2.clkr.hw },
114 { .hw = &pll2.clkr.hw },
128 { .hw = &pll2.clkr.hw },
2847 [PLL2] = &pll2.clkr,
3025 [PLL2] = &pll2.clkr,
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra74x.dtsi139 "pll2_clkctrl", "pll2";
/linux/arch/arm64/boot/dts/sprd/
H A Dums512.dtsi297 pll2: clock-controller@0 { label
/linux/sound/soc/codecs/
H A Dfs210x.c686 ret |= fs210x_reg_write(fs210x, FS210X_A2H_PLLCTRL2, pll_div->pll2); in fs210x_set_hw_params()