Searched refs:pll1rate (Results 1 – 5 of 5) sorted by relevance
| /linux/arch/sh/kernel/cpu/sh2/ |
| H A D | clock-sh7619.c | 19 static const int pll1rate[] = {1,2}; variable
25 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; in master_clk_init()
44 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; in bus_clk_recalc()
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| /linux/arch/sh/kernel/cpu/sh2a/ |
| H A D | clock-sh7206.c | 18 static const int pll1rate[]={1,2,3,4,6,8}; variable
26 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; in master_clk_init()
45 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; in bus_clk_recalc()
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| H A D | clock-sh7203.c | 21 static const int pll1rate[]={8,12,16,0}; variable
29 clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult; in master_clk_init()
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| H A D | clock-sh7201.c | 18 static const int pll1rate[]={1,2,3,4,6,8}; variable
27 pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; in master_clk_init()
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| H A D | clock-sh7264.c | 24 static const unsigned int pll1rate[] = {8, 12}; variable
44 return rate * pll1rate[(__raw_readw(FRQCR) >> 8) & 1]; in pll_recalc()
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