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Searched refs:pll0 (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/bcma/
H A Ddriver_chipcommon_pmu.c84 u32 pll0, mask; in bcma_pmu2_pll_init0() local
115 pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); in bcma_pmu2_pll_init0()
116 freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> in bcma_pmu2_pll_init0()
137 pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; in bcma_pmu2_pll_init0()
138 pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; in bcma_pmu2_pll_init0()
139 bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); in bcma_pmu2_pll_init0()
353 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) in bcma_pmu_pll_clock() argument
358 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); in bcma_pmu_pll_clock()
370 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); in bcma_pmu_pll_clock()
374 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF); in bcma_pmu_pll_clock()
[all …]
/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpll.txt9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
20 This property is only valid when compatible = "ti,da850-pll0".
42 This child node is only valid when compatible = "ti,da850-pll0".
56 pll0: clock-controller@11000 {
57 compatible = "ti,da850-pll0";
/linux/Documentation/devicetree/bindings/clock/st/
H A Dst,clkgen-pll.txt12 "st,clkgen-pll0"
13 "st,clkgen-pll0-a0"
14 "st,clkgen-pll0-c0"
H A Dst,clkgen.txt51 compatible = "st,clkgen-pll0";
/linux/arch/arc/boot/dts/
H A Dabilis_tb10x.dtsi48 pll0: oscillator { label
51 clock-output-names = "pll0";
56 clocks = <&pll0>;
62 clocks = <&pll0>;
H A Dabilis_tb100.dtsi17 pll0: oscillator { label
H A Dabilis_tb101.dtsi17 pll0: oscillator { label
/linux/arch/arm/boot/dts/st/
H A Dstih407-clock.dtsi70 compatible = "st,clkgen-pll0-a0";
89 clk_s_c0_pll0: clk-s-c0-pll0 {
91 compatible = "st,clkgen-pll0-c0";
H A Dstih410-clock.dtsi75 compatible = "st,clkgen-pll0-a0";
94 clk_s_c0_pll0: clk-s-c0-pll0 {
96 compatible = "st,clkgen-pll0-c0";
H A Dstih418-clock.dtsi75 compatible = "st,clkgen-pll0-a0";
94 clk_s_c0_pll0: clk-s-c0-pll0 {
96 compatible = "st,clkgen-pll0-c0";
/linux/drivers/gpu/drm/tegra/
H A Dhdmi.c44 u32 pll0; member
140 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
155 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
173 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
187 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
201 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
219 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
237 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
256 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
275 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
[all …]
H A Dsor.c367 unsigned int pll0; member
1459 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1461 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
2295 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2298 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2493 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2500 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2778 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2780 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2819 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
[all …]
/linux/drivers/clk/mxs/
H A Dclk-imx28.c133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
/linux/arch/arm/boot/dts/marvell/
H A Ddove-cubox.dts101 /* connect xtal input as source of pll0 and pll1 */
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h209 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
H A Dintel_dpll_mgr.c2073 PORT_PLL_M2_INT_MASK, hw_state->pll0); in bxt_ddi_pll_enable()
2192 hw_state->pll0 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 0)); in bxt_ddi_pll_get_hw_state()
2193 hw_state->pll0 &= PORT_PLL_M2_INT_MASK; in bxt_ddi_pll_get_hw_state()
2336 hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2 >> 22); in bxt_ddi_set_dpll_hw_state()
2369 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, hw_state->pll0) << 22; in bxt_ddi_pll_get_freq()
2465 hw_state->pll0, hw_state->pll1, hw_state->pll2, hw_state->pll3, in bxt_dump_hw_state()
2478 a->pll0 == b->pll0 && in bxt_compare_hw_state()
/linux/drivers/phy/ti/
H A DKconfig49 three clock selects (pll0, pll1, dig) and resets for each of the
/linux/drivers/clk/qcom/
H A Dgcc-mdm9615.c47 static struct clk_pll pll0 = { variable
69 &pll0.clkr.hw,
1615 [PLL0] = &pll0.clkr,
H A Dgcc-ipq806x.c32 static struct clk_pll pll0 = { variable
54 &pll0.clkr.hw,
3067 [PLL0] = &pll0.clkr,
/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850.dtsi135 pll0: clock-controller@11000 { label
136 compatible = "ti,da850-pll0";