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Searched refs:plane_res (Results 1 – 25 of 37) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c984 if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp) in calculate_adjust_recout_for_visual_confirm()
988 *dpp_offset *= pipe_ctx->plane_res.dpp->inst; in calculate_adjust_recout_for_visual_confirm()
1166 pipe_ctx->plane_res.scl_data.recout = shift_rec( in calculate_recout()
1170 &pipe_ctx->plane_res.scl_data.recout, in calculate_recout()
1174 memset(&pipe_ctx->plane_res.scl_data.recout, 0, in calculate_recout()
1195 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( in calculate_scaling_ratios()
1198 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( in calculate_scaling_ratios()
1203 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; in calculate_scaling_ratios()
1205 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; in calculate_scaling_ratios()
1207 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( in calculate_scaling_ratios()
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H A Ddc_stream.c417 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || in program_cursor_position()
419 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || in program_cursor_position()
420 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) in program_cursor_position()
513 pipe_ctx->plane_res.hubp->mpcc_id); in dc_stream_program_cursor_position()
849 hubp = pipe_ctx->plane_res.hubp; in dc_stream_set_dynamic_metadata()
H A Ddc_surface.c76 if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp) in dc_plane_get_pipe_mask()
77 pipe_mask |= 1 << pipe_ctx->plane_res.hubp->inst; in dc_plane_get_pipe_mask()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c725 pipe_ctx->plane_res.hubp = hubp; in dcn35_init_pipes()
726 pipe_ctx->plane_res.dpp = dpp; in dcn35_init_pipes()
727 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn35_init_pipes()
734 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn35_init_pipes()
745 pipe_ctx->plane_res.hubp = NULL; in dcn35_init_pipes()
819 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn35_enable_plane()
822 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); in dcn35_enable_plane()
825 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); in dcn35_enable_plane()
842 …pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &a… in dcn35_enable_plane()
849 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) in dcn35_enable_plane()
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/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c318 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { in pipe_ctx_to_e2e_pipe_params()
333 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
341 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
342 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height; in pipe_ctx_to_e2e_pipe_params()
343 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
344 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
398 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params()
399 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
400 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
401 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c287 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; in dce110_set_input_transfer_func()
610 struct transform *xfm = pipe_ctx->plane_res.xfm; in dce110_set_output_transfer_func()
1470 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) in program_scaler()
1480 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( in program_scaler()
1481 pipe_ctx->plane_res.xfm, in program_scaler()
1482 pipe_ctx->plane_res.scl_data.lb_params.depth, in program_scaler()
1499 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in program_scaler()
1500 &pipe_ctx->plane_res.scl_data); in program_scaler()
1700 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; in dce110_apply_single_controller_ctx_to_hw()
2057 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( in dce110_set_displaymarks()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c95 unsigned int mpcc_id = pipe_ctx->plane_res.mpcc_inst; in dcn401_program_gamut_remap()
383 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn401_get_mcm_lut_xable_from_pipe_ctx()
413 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn401_populate_mcm_luts()
414 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn401_populate_mcm_luts()
607 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn401_trigger_3dlut_dma_load()
617 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn401_set_mcm_luts()
618 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn401_set_mcm_luts()
671 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn401_set_output_transfer_func()
1079 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn401_set_cursor_position()
1080 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn401_set_cursor_position()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c302 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) in dcn20_set_flip_control_gsl()
303 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( in dcn20_set_flip_control_gsl()
304 pipe_ctx->plane_res.hubp, flip_immediate); in dcn20_set_flip_control_gsl()
382 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { in dcn20_program_triple_buffer()
383 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( in dcn20_program_triple_buffer()
384 pipe_ctx->plane_res.hubp, in dcn20_program_triple_buffer()
698 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn20_plane_atomic_disable()
699 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn20_plane_atomic_disable()
721 pipe_ctx->plane_res.dpp, in dcn20_plane_atomic_disable()
722 pipe_ctx->plane_res.hubp); in dcn20_plane_atomic_disable()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c152 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( in dcn201_update_plane_addr()
153 pipe_ctx->plane_res.hubp, in dcn201_update_plane_addr()
316 pipe_ctx->plane_res.hubp = hubp; in dcn201_init_hw()
317 pipe_ctx->plane_res.dpp = dpp; in dcn201_init_hw()
318 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn201_init_hw()
326 res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn201_init_hw()
349 pipe_ctx->plane_res.hubp = NULL; in dcn201_init_hw()
383 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn201_plane_atomic_disconnect()
384 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn201_plane_atomic_disconnect()
414 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn201_plane_atomic_disconnect()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c816 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_did_underflow_occur()
1371 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1384 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1394 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1406 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1446 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_plane_atomic_disconnect()
1447 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn10_plane_atomic_disconnect()
1464 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_plane_atomic_disconnect()
1524 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_plane_atomic_disable()
1525 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn10_plane_atomic_disable()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1491 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1492 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1493 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1494 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1495 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1496 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; in dcn20_split_stream_for_odm()
1547 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
1548 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
1549 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
1550 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c237 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut()
259 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_mpc_shaper_3dlut()
260 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_mpc_shaper_3dlut()
321 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_input_transfer_func()
362 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_program_gamut_remap()
376 pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, in dcn30_program_gamut_remap()
398 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_output_transfer_func()
612 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dcn30_program_all_writeback_pipes_in_tree()
889 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn30_program_dmdata_engine()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource_helpers.c44 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn32_helper_calculate_mall_bytes_for_cursor()
133 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_merge_pipes_for_subvp()
147 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_merge_pipes_for_subvp()
H A Ddcn32_resource.c2764 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2765 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2766 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2767 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2823 free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2824 free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2825 free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2826 free_pipe->plane_res.mpcc_inst = in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2854 free_pipe->plane_res.mi = pool->mis[free_pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_opp_head()
2855 free_pipe->plane_res.hubp = pool->hubps[free_pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_opp_head()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_translation_helper.c482 temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps; in get_scaler_data_for_plane()
493 return &temp_pipe->plane_res.scl_data; in get_scaler_data_for_plane()
887 mcache_pipe_config->plane0.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x; in dml21_get_pipe_mcache_config()
888 mcache_pipe_config->plane0.viewport_width = pipe_ctx->plane_res.scl_data.viewport.width; in dml21_get_pipe_mcache_config()
890 mcache_pipe_config->plane1.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport_c.x; in dml21_get_pipe_mcache_config()
891 mcache_pipe_config->plane1.viewport_width = pipe_ctx->plane_res.scl_data.viewport_c.width; in dml21_get_pipe_mcache_config()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_trace.h31 pipe_ctx->stream, &pipe_ctx->plane_res, \
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr.c169 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control( in ramp_up_dispclk_with_dpp()
170 pipe_ctx->plane_res.dpp, in ramp_up_dispclk_with_dpp()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddmub_psr.c341 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dmub_psr_copy_settings()
343 if (pipe_ctx->plane_res.dpp) in dmub_psr_copy_settings()
344 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; in dmub_psr_copy_settings()
H A Ddmub_replay.c153 if (pipe_ctx->plane_res.dpp) in dmub_replay_copy_settings()
154 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; in dmub_replay_copy_settings()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c449 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mpc_shaper_3dlut()
450 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_mpc_shaper_3dlut()
486 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mcm_luts()
487 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_mcm_luts()
535 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_input_transfer_func()
573 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_output_transfer_func()
617 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_update_force_pstate()
637 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_update_force_pstate()
682 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_update_mall_sel()
742 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_program_mall_pipe_config()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1532 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1533 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1534 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1535 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1536 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1537 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn30_split_stream_for_mpc_or_odm()
1742 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn30_internal_validate_bw()
1757 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn30_internal_validate_bw()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c323 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn32_update_clocks_update_dpp_dto()
325 if (context->res_ctx.pipe_ctx[i].plane_res.dpp) in dcn32_update_clocks_update_dpp_dto()
326 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; in dcn32_update_clocks_update_dpp_dto()
327 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) { in dcn32_update_clocks_update_dpp_dto()
332 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) { in dcn32_update_clocks_update_dpp_dto()
/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_panel_replay.c308 if (pipe_ctx->plane_res.dpp) in dp_pr_copy_settings()
309 cmd.pr_copy_settings.data.dpp_inst = pipe_ctx->plane_res.dpp->inst; in dp_pr_copy_settings()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c1022 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn201_acquire_free_pipe_for_layer()
1023 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn201_acquire_free_pipe_for_layer()
1024 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn201_acquire_free_pipe_for_layer()
1025 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn201_acquire_free_pipe_for_layer()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c291 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn35_update_clocks_update_dpp_dto()
293 if (context->res_ctx.pipe_ctx[i].plane_res.dpp) in dcn35_update_clocks_update_dpp_dto()
294 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; in dcn35_update_clocks_update_dpp_dto()
295 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) { in dcn35_update_clocks_update_dpp_dto()
300 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) { in dcn35_update_clocks_update_dpp_dto()
317 struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp; in dcn35_update_clocks_update_dpp_dto()

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