| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/ |
| H A D | dml2_pmo_dcn6_stage_optimizers.c | 410 unsigned int plane_index, stream_index; in dcn6_update_worksheet_for_pstate_admissibility() local
483 for (plane_index = 0; plane_index < display_config->num_planes; plane_index++) { in dcn6_update_worksheet_for_pstate_admissibility()
484 if (display_config->plane_descriptors[plane_index].stream_index != stream_index) { in dcn6_update_worksheet_for_pstate_admissibility()
489 if (worksheet->cur.config.max_vactive_det_fill_delay_us[plane_index][pstate_type] > 0.0) { in dcn6_update_worksheet_for_pstate_admissibility()
491 (double)worksheet->cur.config.max_vactive_det_fill_delay_us[plane_index][pstate_type], in dcn6_update_worksheet_for_pstate_admissibility()
499 (double)worksheet->cur.config.reserved_vblank_time_ns[plane_index], in dcn6_update_worksheet_for_pstate_admissibility()
502 …ll_delay_us > 0 && worksheet->cur.config.max_vactive_det_fill_delay_us[plane_index][pstate_type] =… in dcn6_update_worksheet_for_pstate_admissibility()
503 …et_fill_delay_us < worksheet->cur.config.max_vactive_det_fill_delay_us[plane_index][pstate_type] || in dcn6_update_worksheet_for_pstate_admissibility()
504 …(reserved_vblank_time_ns > 0 && worksheet->cur.config.reserved_vblank_time_ns[plane_index] == 0) || in dcn6_update_worksheet_for_pstate_admissibility()
505 reserved_vblank_time_ns > worksheet->cur.config.reserved_vblank_time_ns[plane_index]) { in dcn6_update_worksheet_for_pstate_admissibility()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_dc_resource_mgmt.c | 59 unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id) in get_plane_id() argument
71 (!is_plane_duplicate || (j == plane_index))) { in get_plane_id()
656 int plane_index, in assign_pipes_to_plane() argument
668 if (!get_plane_id(ctx, state, plane, stream->stream_id, plane_index, &plane_id)) { in assign_pipes_to_plane()
715 …plane_state *plane, const struct dc_plane_pipe_pool *pool, unsigned int stream_id, int plane_index) in free_unused_pipes_for_plane() argument
724 …dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx] == plane_index) && in free_unused_pipes_for_plane()
770 int plane_index, struct dc_pipe_mapping_scratch *scratch, const struct dc_state *existing_state) in map_pipes_for_plane() argument
777 if (!get_plane_id(ctx, state, plane, stream->stream_id, plane_index, &plane_id)) { in map_pipes_for_plane()
783 scratch->mpc_info.mpc_factor, plane_index, &scratch->pipe_pool, existing_state); in map_pipes_for_plane()
803 …free_unused_pipes_for_plane(ctx, state, plane, &scratch->pipe_pool, stream->stream_id, plane_index… in map_pipes_for_plane()
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| H A D | dml2_translation_helper.c | 1160 unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id) in get_plane_id() argument
1172 (!is_plane_duplicate || (j == plane_index))) { in get_plane_id()
1184 …te *context, const struct dml_display_cfg_st *dml_dispcfg, unsigned int stream_id, int plane_index) in map_plane_to_dml_display_cfg() argument
1191 if (!get_plane_id(context->bw_ctx.dml2, context, plane, stream_id, plane_index, &plane_id)) { in map_plane_to_dml_display_cfg()
1210 unsigned int plane_index = 0; in dml2_populate_pipe_to_plane_index_mapping() local
1228 dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index[pipe_index] = plane_index; in dml2_populate_pipe_to_plane_index_mapping()
1229 plane_index++; in dml2_populate_pipe_to_plane_index_mapping()
1236 plane_index = 0; in dml2_populate_pipe_to_plane_index_mapping()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_utils.c | 613 unsigned int stream_index, plane_index; in dml2_core_utils_expand_implict_subvp() local
652 for (plane_index = 0; plane_index < display_cfg->display_config.num_planes; plane_index++) { in dml2_core_utils_expand_implict_subvp()
653 main_plane = &display_cfg->display_config.plane_descriptors[plane_index]; in dml2_core_utils_expand_implict_subvp()
662 …ratch->phantom_plane_index_to_main_plane_index[svp_expanded_display_cfg->num_planes] = plane_index; in dml2_core_utils_expand_implict_subvp()
663 …scratch->main_plane_index_to_phantom_plane_index[plane_index] = svp_expanded_display_cfg->num_plan… in dml2_core_utils_expand_implict_subvp()
669 …svp_expanded_display_cfg->plane_descriptors[plane_index].overrides.legacy_svp_config = dml2_svp_mo… in dml2_core_utils_expand_implict_subvp()
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| H A D | dml2_core_dcn5_calcs_dchub.c | 1635 unsigned int plane_index; in dcn5_calculate_bytes_to_fetch_required_to_hide_latency() local
1638 for (plane_index = 0; plane_index < p->num_active_planes; plane_index++) { in dcn5_calculate_bytes_to_fetch_required_to_hide_latency()
1639 stream_index = p->display_cfg->plane_descriptors[plane_index].stream_index; in dcn5_calculate_bytes_to_fetch_required_to_hide_latency()
1641 dst_lines_to_hide = (unsigned int)math_ceil(p->latency_to_hide_us[plane_index] / in dcn5_calculate_bytes_to_fetch_required_to_hide_latency()
1645 …src_lines_to_hide_l = (unsigned int)math_ceil2(p->display_cfg->plane_descriptors[plane_index].comp… in dcn5_calculate_bytes_to_fetch_required_to_hide_latency()
1646 p->swath_height_l[plane_index]); in dcn5_calculate_bytes_to_fetch_required_to_hide_latency()
1647 …s_required_l[plane_index] = src_lines_to_hide_l * p->num_of_dpp[plane_index] * p->swath_width_l[pl… in dcn5_calculate_bytes_to_fetch_required_to_hide_latency()
1649 …src_lines_to_hide_c = (unsigned int)math_ceil2(p->display_cfg->plane_descriptors[plane_index].comp… in dcn5_calculate_bytes_to_fetch_required_to_hide_latency()
1650 p->swath_height_c[plane_index]); in dcn5_calculate_bytes_to_fetch_required_to_hide_latency()
1651 …s_required_c[plane_index] = src_lines_to_hide_c * p->num_of_dpp[plane_index] * p->swath_width_c[pl… in dcn5_calculate_bytes_to_fetch_required_to_hide_latency()
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| H A D | dml2_core_dcn5_funcs_mode_programming.c | 1463 int plane_index) in dcn5_populate_fams2_programming() argument
1466 const struct dml2_plane_parameters *plane_descriptor = &disp_cfg->plane_descriptors[plane_index]; in dcn5_populate_fams2_programming()
1608 unsigned int plane_index; in dcn5_pack_mode_programming_params() local
1632 for (plane_index = 0; plane_index < programming->display_config.num_planes; plane_index++) { in dcn5_pack_mode_programming_params()
1633 programming->plane_programming[plane_index].num_dpps_required = mode_lib->mp.NoOfDPP[plane_index]; in dcn5_pack_mode_programming_params()
1638 …gramming->plane_programming[plane_index].uclk_pstate_support_method = mode_prog->uclk_params->psta… in dcn5_pack_mode_programming_params()
1640 programming->plane_programming[plane_index].uclk_pstate_support_method = dml2_pstate_method_na; in dcn5_pack_mode_programming_params()
1642 …if (mode_lib->mp.MaxActiveDRAMClockChangeLatencySupported[plane_index] >= utm_soc_bb->power_manage… in dcn5_pack_mode_programming_params()
1643 …programming->plane_programming[plane_index].uclk_pstate_support_method = dml2_pstate_method_vactiv… in dcn5_pack_mode_programming_params()
1644 …else if (mode_lib->mp.TWait[plane_index] >= utm_soc_bb->power_management_parameters.dram_clk_chang… in dcn5_pack_mode_programming_params()
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| H A D | dml2_core_dcn6_calcs_dchub.c | 1649 unsigned int plane_index; in dcn6_calculate_excess_vactive_bandwidth_required() local
1652 for (plane_index = 0; plane_index < display_cfg->num_planes; plane_index++) { in dcn6_calculate_excess_vactive_bandwidth_required()
1653 excess_vactive_fill_bw_l[plane_index] = 0.0; in dcn6_calculate_excess_vactive_bandwidth_required()
1654 excess_vactive_fill_bw_c[plane_index] = 0.0; in dcn6_calculate_excess_vactive_bandwidth_required()
1657 …if (display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[pstate_typ… in dcn6_calculate_excess_vactive_bandwidth_required()
1658 excess_vactive_fill_bw_l[plane_index] = math_max2( in dcn6_calculate_excess_vactive_bandwidth_required()
1659 (double)bytes_required_l[pstate_type][plane_index] / in dcn6_calculate_excess_vactive_bandwidth_required()
1660 …(double)display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[pstate… in dcn6_calculate_excess_vactive_bandwidth_required()
1661 excess_vactive_fill_bw_l[plane_index]); in dcn6_calculate_excess_vactive_bandwidth_required()
1662 excess_vactive_fill_bw_c[plane_index] = math_max2( in dcn6_calculate_excess_vactive_bandwidth_required()
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| /linux/drivers/net/ethernet/mellanox/mlx5/core/ |
| H A D | port.c | 148 u8 local_port, u8 plane_index) in mlx5_query_port_ptys() argument
153 MLX5_SET(ptys_reg, in, plane_ind, plane_index); in mlx5_query_port_ptys()
172 u16 *proto_oper, u8 local_port, u8 plane_index) in mlx5_query_ib_port_oper() argument
178 local_port, plane_index); in mlx5_query_ib_port_oper()
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| /linux/drivers/infiniband/hw/mlx5/ |
| H A D | cmd.c | 199 MLX5_SET(mad_ifc_in, in, plane_index, port); in mlx5_cmd_mad_ifc()
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| H A D | main.c | 1467 u8 vl_hw_cap, plane_index = 0; in mlx5_query_hca_port() local
1482 plane_index = port; in mlx5_query_hca_port()
1516 &props->active_speed, port, plane_index); in mlx5_query_hca_port()
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