/linux/drivers/gpu/drm/i915/display/ |
H A D | intel_sprite_regs.h | 230 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ argument 231 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) 232 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ argument 233 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) 237 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) argument 266 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) argument 270 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) argument 274 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) argument 282 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) argument 290 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) argument [all …]
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H A D | skl_universal_plane.c | 249 enum plane_id plane_id) in icl_is_nv12_y_plane() argument 252 icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id); in icl_is_nv12_y_plane() 260 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) in icl_is_hdr_plane() argument 263 icl_hdr_plane_mask() & BIT(plane_id); in icl_is_hdr_plane() 612 enum plane_id plane_id = plane->id; in icl_program_input_csc() local 654 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), in icl_program_input_csc() 656 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), in icl_program_input_csc() 658 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), in icl_program_input_csc() 660 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), in icl_program_input_csc() 662 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), in icl_program_input_csc() [all …]
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H A D | skl_universal_plane.h | 19 enum plane_id; 23 enum pipe pipe, enum plane_id plane_id); 36 enum plane_id plane_id); 38 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
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H A D | intel_dpt_common.c | 18 enum plane_id plane_id; in intel_dpt_configure() local 20 for_each_plane_id_on_crtc(crtc, plane_id) { in intel_dpt_configure() 21 if (plane_id == PLANE_CURSOR) in intel_dpt_configure() 24 intel_de_rmw(i915, PLANE_CHICKEN(pipe, plane_id), in intel_dpt_configure()
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H A D | skl_watermark.c | 353 enum plane_id plane_id; in skl_crtc_can_enable_sagv() local 365 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_crtc_can_enable_sagv() 367 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv() 387 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_crtc_can_enable_sagv() 389 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv() 405 enum plane_id plane_id; in tgl_crtc_can_enable_sagv() local 410 for_each_plane_id_on_crtc(crtc, plane_id) { in tgl_crtc_can_enable_sagv() 412 &crtc_state->wm.skl.optimal.planes[plane_id]; in tgl_crtc_can_enable_sagv() 796 const enum plane_id plane_id, in skl_ddb_get_hw_plane_state() argument 803 if (plane_id == PLANE_CURSOR) { in skl_ddb_get_hw_plane_state() [all …]
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H A D | intel_sprite.c | 72 enum plane_id plane_id = plane->id; in chv_sprite_update_csc() local 103 intel_de_write_fw(display, SPCSCYGOFF(plane_id), in chv_sprite_update_csc() 105 intel_de_write_fw(display, SPCSCCBOFF(plane_id), in chv_sprite_update_csc() 107 intel_de_write_fw(display, SPCSCCROFF(plane_id), in chv_sprite_update_csc() 110 intel_de_write_fw(display, SPCSCC01(plane_id), in chv_sprite_update_csc() 112 intel_de_write_fw(display, SPCSCC23(plane_id), in chv_sprite_update_csc() 114 intel_de_write_fw(display, SPCSCC45(plane_id), in chv_sprite_update_csc() 116 intel_de_write_fw(display, SPCSCC67(plane_id), in chv_sprite_update_csc() 118 intel_de_write_fw(display, SPCSCC8(plane_id), SPCSC_C0(csc[8])); in chv_sprite_update_csc() 120 intel_de_write_fw(display, SPCSCYGICLAMP(plane_id), in chv_sprite_update_csc() [all …]
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H A D | i9xx_wm.c | 918 static int g4x_plane_fifo_size(enum plane_id plane_id, int level) in g4x_plane_fifo_size() argument 934 switch (plane_id) { in g4x_plane_fifo_size() 942 MISSING_CASE(plane_id); in g4x_plane_fifo_size() 1017 int level, enum plane_id plane_id, u16 value) in g4x_raw_plane_wm_set() argument 1025 dirty |= raw->plane[plane_id] != value; in g4x_raw_plane_wm_set() 1026 raw->plane[plane_id] = value; in g4x_raw_plane_wm_set() 1060 enum plane_id plane_id = plane->id; in g4x_raw_plane_wm_compute() local 1065 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0); in g4x_raw_plane_wm_compute() 1066 if (plane_id == PLANE_PRIMARY) in g4x_raw_plane_wm_compute() 1076 max_wm = g4x_plane_fifo_size(plane_id, level); in g4x_raw_plane_wm_compute() [all …]
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H A D | intel_fbc_regs.h | 66 #define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id)) argument
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H A D | intel_display_debugfs.c | 708 enum plane_id plane_id; in i915_ddb_info() local 712 for_each_plane_id_on_crtc(crtc, plane_id) { in i915_ddb_info() 713 entry = &crtc_state->wm.skl.plane_ddb[plane_id]; in i915_ddb_info() 714 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1, in i915_ddb_info()
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/linux/drivers/gpu/drm/kmb/ |
H A D | kmb_plane.c | 72 int plane_id = kmb_plane->id; in check_pixel_format() local 76 init_disp_cfg = kmb->init_disp_cfg[plane_id]; in check_pixel_format() 98 int plane_id = kmb_plane->id; in kmb_plane_atomic_check() local 106 init_disp_cfg = kmb->init_disp_cfg[plane_id]; in kmb_plane_atomic_check() 145 int plane_id = kmb_plane->id; in kmb_plane_atomic_disable() local 150 if (WARN_ON(plane_id >= KMB_MAX_PLANES)) in kmb_plane_atomic_disable() 153 switch (plane_id) { in kmb_plane_atomic_disable() 155 kmb->plane_status[plane_id].ctrl = LCD_CTRL_VL1_ENABLE; in kmb_plane_atomic_disable() 158 kmb->plane_status[plane_id].ctrl = LCD_CTRL_VL2_ENABLE; in kmb_plane_atomic_disable() 162 kmb->plane_status[plane_id].disable = true; in kmb_plane_atomic_disable() [all …]
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H A D | kmb_drv.c | 207 int plane_id, dma0_state, dma1_state; in handle_lcd_irq() local 223 for (plane_id = LAYER_0; in handle_lcd_irq() 224 plane_id < KMB_MAX_PLANES; plane_id++) { in handle_lcd_irq() 225 if (kmb->plane_status[plane_id].disable) { in handle_lcd_irq() 228 (plane_id), in handle_lcd_irq() 232 kmb->plane_status[plane_id].ctrl); in handle_lcd_irq() 247 kmb->plane_status[plane_id].disable = false; in handle_lcd_irq()
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
H A D | dml21_utils.h | 19 int dml21_find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id); 20 …plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id); 45 unsigned int dml21_get_dc_plane_idx_from_plane_id(unsigned int plane_id);
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H A D | dml21_utils.c | 25 int dml21_find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id) in dml21_find_dml_pipe_idx_by_plane_id() argument 29 …dx_to_plane_id_valid[i] && ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] == plane_id) in dml21_find_dml_pipe_idx_by_plane_id() 36 …_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id) in dml21_get_plane_id() argument 40 if (!plane_id) in dml21_get_plane_id() 46 *plane_id = (i << 16) | j; in dml21_get_plane_id() 55 unsigned int dml21_get_dc_plane_idx_from_plane_id(unsigned int plane_id) in dml21_get_dc_plane_idx_from_plane_id() argument 57 return 0xffff & plane_id; in dml21_get_dc_plane_idx_from_plane_id()
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/linux/drivers/gpu/drm/amd/display/dc/dml2/ |
H A D | dml2_utils.c | 205 static int find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id) in find_dml_pipe_idx_by_plane_id() argument 209 …ane_id_valid[i] && ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] == plane_id) in find_dml_pipe_idx_by_plane_id() 217 unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id) in get_plane_id() argument 222 if (!plane_id) in get_plane_id() 230 *plane_id = (i << 16) | j; in get_plane_id() 281 unsigned int dc_pipe_ctx_index, dml_pipe_idx, plane_id; in dml2_calculate_rq_and_dlg_params() local 307 …g.dml_pipe_idx_to_plane_index[context->res_ctx.pipe_ctx[dc_pipe_ctx_index].pipe_idx], &plane_id)) { in dml2_calculate_rq_and_dlg_params() 308 dml_pipe_idx = find_dml_pipe_idx_by_plane_id(in_ctx, plane_id); in dml2_calculate_rq_and_dlg_params() 513 unsigned int i = 0, dml_pipe_idx = 0, plane_id = 0; in dml2_verify_det_buffer_configuration() local 524 …_pipe_mapping.dml_pipe_idx_to_plane_index[display_state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id)) in dml2_verify_det_buffer_configuration() [all …]
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H A D | dml2_translation_helper.c | 1106 unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id) in get_plane_id() argument 1111 if (!plane_id) in get_plane_id() 1119 *plane_id = (i << 16) | j; in get_plane_id() 1132 unsigned int plane_id; in map_plane_to_dml_display_cfg() local 1136 if (!get_plane_id(context->bw_ctx.dml2, context, plane, stream_id, plane_index, &plane_id)) { in map_plane_to_dml_display_cfg() 1142 …lane_id_valid[i] && dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i] == plane_id) { in map_plane_to_dml_display_cfg()
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/linux/drivers/gpu/drm/i915/gvt/ |
H A D | dmabuf.c | 257 int plane_id) in vgpu_get_plane_info() argument 265 if (plane_id == DRM_PLANE_TYPE_PRIMARY) { in vgpu_get_plane_info() 295 } else if (plane_id == DRM_PLANE_TYPE_CURSOR) { in vgpu_get_plane_info() 317 gvt_vgpu_err("invalid plane id:%d\n", plane_id); in vgpu_get_plane_info()
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/linux/drivers/media/platform/nvidia/tegra-vde/ |
H A D | h264.c | 674 unsigned int plane_id, in tegra_vde_validate_vb_size() argument 677 u64 offset = vb->planes[plane_id].data_offset; in tegra_vde_validate_vb_size() 680 if (offset + min_size > vb2_plane_size(vb, plane_id)) { in tegra_vde_validate_vb_size() 682 plane_id, vb2_plane_size(vb, plane_id), offset, min_size); in tegra_vde_validate_vb_size()
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/linux/drivers/gpu/drm/msm/disp/dpu1/ |
H A D | dpu_trace.h | 651 TP_PROTO(uint32_t crtc_id, uint32_t plane_id, 655 TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, 659 __field( uint32_t, plane_id ) 673 __entry->plane_id = plane_id; 689 __entry->crtc_id, __entry->plane_id, __entry->fb_id,
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/linux/include/uapi/drm/ |
H A D | drm_mode.h | 297 __u32 plane_id; member 334 __u32 plane_id; member
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H A D | i915_drm.h | 1926 __u32 plane_id; member
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/linux/drivers/gpu/drm/ |
H A D | drm_plane.c | 836 plane = drm_plane_find(dev, file_priv, plane_resp->plane_id); in drm_mode_getplane() 856 plane_resp->plane_id = plane->base.id; in drm_mode_getplane() 1124 plane = drm_plane_find(dev, file_priv, plane_req->plane_id); in drm_mode_setplane() 1127 plane_req->plane_id); in drm_mode_setplane()
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/linux/drivers/gpu/drm/ingenic/ |
H A D | ingenic-drm-drv.c | 663 unsigned int width, height, cpp, next_id, plane_id; in ingenic_drm_plane_atomic_update() local 675 plane_id = !!(priv->soc_info->has_osd && plane != &priv->f0); in ingenic_drm_plane_atomic_update() 683 next_id = (priv_state && priv_state->use_palette) ? HWDESC_PALETTE : plane_id; in ingenic_drm_plane_atomic_update() 685 hwdesc = &priv->dma_hwdescs->hwdesc[plane_id]; in ingenic_drm_plane_atomic_update()
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/linux/drivers/gpu/drm/i915/ |
H A D | i915_reg.h | 1736 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MA… argument 2237 #define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1) argument 2260 #define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1) argument 2534 #define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \ argument 2535 REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
H A D | dcn10_hwseq.c | 792 int plane_id) in power_on_plane_resources() argument 797 hws->funcs.dpp_root_clock_control(hws, plane_id, true); in power_on_plane_resources() 804 hws->funcs.dpp_pg_control(hws, plane_id, true); in power_on_plane_resources() 807 hws->funcs.hubp_pg_control(hws, plane_id, true); in power_on_plane_resources() 812 "Un-gated front end for pipe %d\n", plane_id); in power_on_plane_resources()
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/linux/tools/include/uapi/drm/ |
H A D | i915_drm.h | 1926 __u32 plane_id; member
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