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Searched refs:plane_id (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_sprite_regs.h230 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ argument
231 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
232 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ argument
233 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
237 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) argument
266 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) argument
270 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) argument
274 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) argument
282 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) argument
290 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) argument
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H A Dintel_dbuf_bw.c99 enum plane_id plane_id, in skl_plane_calc_dbuf_bw() argument
113 dbuf_bw->active_planes[slice] |= BIT(plane_id); in skl_plane_calc_dbuf_bw()
122 enum plane_id plane_id; in skl_crtc_calc_dbuf_bw() local
129 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_crtc_calc_dbuf_bw()
134 if (plane_id == PLANE_CURSOR) in skl_crtc_calc_dbuf_bw()
137 skl_plane_calc_dbuf_bw(dbuf_bw, crtc, plane_id, in skl_crtc_calc_dbuf_bw()
138 &crtc_state->wm.skl.plane_ddb[plane_id], in skl_crtc_calc_dbuf_bw()
139 crtc_state->data_rate[plane_id]); in skl_crtc_calc_dbuf_bw()
142 skl_plane_calc_dbuf_bw(dbuf_bw, crtc, plane_id, in skl_crtc_calc_dbuf_bw()
143 &crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_crtc_calc_dbuf_bw()
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H A Dintel_display_irq.c100 bool (*handle)(struct intel_crtc *crtc, enum plane_id plane_id);
102 enum plane_id plane_id; member
105 static bool handle_plane_fault(struct intel_crtc *crtc, enum plane_id plane_id) in handle_plane_fault() argument
111 plane = intel_crtc_get_plane(crtc, plane_id); in handle_plane_fault()
137 if (handler->handle(crtc, handler->plane_id)) in intel_pipe_fault_irq_handler()
744 { .fault = ERR_INT_SPRITE_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, },
745 { .fault = ERR_INT_PRIMARY_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, },
746 { .fault = ERR_INT_CURSOR_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, },
747 { .fault = ERR_INT_SPRITE_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, },
748 { .fault = ERR_INT_PRIMARY_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, },
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H A Dskl_watermark.c309 enum plane_id plane_id; in skl_crtc_can_enable_sagv() local
321 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_crtc_can_enable_sagv()
323 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
343 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_crtc_can_enable_sagv()
345 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
361 enum plane_id plane_id; in tgl_crtc_can_enable_sagv() local
366 for_each_plane_id_on_crtc(crtc, plane_id) { in tgl_crtc_can_enable_sagv()
368 &crtc_state->wm.skl.optimal.planes[plane_id]; in tgl_crtc_can_enable_sagv()
682 const enum plane_id plane_id, in skl_ddb_get_hw_plane_state() argument
690 if (plane_id == PLANE_CURSOR) { in skl_ddb_get_hw_plane_state()
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H A Dintel_plane.c746 intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id) in intel_crtc_get_plane() argument
752 if (plane->id == plane_id) in intel_crtc_get_plane()
825 enum plane_id plane_id = plane->id; in skl_next_plane_to_commit() local
828 !(*update_mask & BIT(plane_id))) in skl_next_plane_to_commit()
831 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id], in skl_next_plane_to_commit()
832 ddb, I915_MAX_PLANES, plane_id) || in skl_next_plane_to_commit()
833 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_next_plane_to_commit()
834 ddb_y, I915_MAX_PLANES, plane_id)) in skl_next_plane_to_commit()
837 *update_mask &= ~BIT(plane_id); in skl_next_plane_to_commit()
838 ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id]; in skl_next_plane_to_commit()
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H A Dintel_crtc.c832 enum plane_id plane_id; in intel_crtc_bw_data_rate() local
834 for_each_plane_id_on_crtc(crtc, plane_id) { in intel_crtc_bw_data_rate()
839 if (plane_id == PLANE_CURSOR) in intel_crtc_bw_data_rate()
842 data_rate += crtc_state->data_rate[plane_id]; in intel_crtc_bw_data_rate()
845 data_rate += crtc_state->data_rate_y[plane_id]; in intel_crtc_bw_data_rate()
H A Dintel_display_limits.h72 enum plane_id { enum
H A Dintel_display_types.h1578 enum plane_id id;
H A Dintel_color.c3858 enum plane_id plane = to_intel_plane(state->plane)->id; in xelpd_load_plane_csc_matrix()
3953 enum plane_id plane = to_intel_plane(state->plane)->id; in xelpd_program_plane_pre_csc_lut()
4006 enum plane_id plane = to_intel_plane(state->plane)->id; in xelpd_program_plane_post_csc_lut()
/linux/drivers/gpu/drm/sti/
H A Dsti_mixer.c239 int plane_id, depth = plane->drm_plane.state->normalized_zpos; in sti_mixer_set_plane_depth() local
245 plane_id = GAM_DEPTH_GDP0_ID; in sti_mixer_set_plane_depth()
248 plane_id = GAM_DEPTH_GDP1_ID; in sti_mixer_set_plane_depth()
251 plane_id = GAM_DEPTH_GDP2_ID; in sti_mixer_set_plane_depth()
254 plane_id = GAM_DEPTH_GDP3_ID; in sti_mixer_set_plane_depth()
257 plane_id = GAM_DEPTH_VID0_ID; in sti_mixer_set_plane_depth()
271 if ((val & mask) == plane_id << (3 * i)) in sti_mixer_set_plane_depth()
276 plane_id = plane_id << (3 * depth); in sti_mixer_set_plane_depth()
281 plane_id, mask); in sti_mixer_set_plane_depth()
284 val |= plane_id; in sti_mixer_set_plane_depth()
/linux/drivers/gpu/drm/i915/gvt/
H A Ddmabuf.c258 int plane_id) in vgpu_get_plane_info() argument
266 if (plane_id == DRM_PLANE_TYPE_PRIMARY) { in vgpu_get_plane_info()
296 } else if (plane_id == DRM_PLANE_TYPE_CURSOR) { in vgpu_get_plane_info()
318 gvt_vgpu_err("invalid plane id:%d\n", plane_id); in vgpu_get_plane_info()
H A Dhandlers.c1078 enum plane_id plane = REG_50080_TO_PLANE(offset); in reg50080_mmio_write()
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_trace.h651 TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
655 TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx,
659 __field( uint32_t, plane_id )
673 __entry->plane_id = plane_id;
689 __entry->crtc_id, __entry->plane_id, __entry->fb_id,
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_translation_helper.c644 …state *context, unsigned int stream_id, const struct dc_plane_state *plane, unsigned int *plane_id) in dml21_wrapper_get_plane_id() argument
648 if (!plane_id) in dml21_wrapper_get_plane_id()
655 *plane_id = (i << 16) | j; in dml21_wrapper_get_plane_id()
683 unsigned int plane_id; in map_plane_to_dml21_display_cfg() local
687 if (!dml21_wrapper_get_plane_id(context, stream_id, plane, &plane_id)) { in map_plane_to_dml21_display_cfg()
693 …_to_plane_id_valid[i] && dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i] == plane_id) { in map_plane_to_dml21_display_cfg()
/linux/include/uapi/drm/
H A Ddrm_mode.h297 __u32 plane_id; member
334 __u32 plane_id; member
H A Di915_drm.h1926 __u32 plane_id; member
/linux/drivers/gpu/drm/
H A Ddrm_plane.c863 plane = drm_plane_find(dev, file_priv, plane_resp->plane_id); in drm_mode_getplane()
883 plane_resp->plane_id = plane->base.id; in drm_mode_getplane()
1151 plane = drm_plane_find(dev, file_priv, plane_req->plane_id); in drm_mode_setplane()
1154 plane_req->plane_id); in drm_mode_setplane()
/linux/drivers/gpu/drm/ingenic/
H A Dingenic-drm-drv.c668 unsigned int width, height, cpp, next_id, plane_id; in ingenic_drm_plane_atomic_update() local
680 plane_id = !!(priv->soc_info->has_osd && plane != &priv->f0); in ingenic_drm_plane_atomic_update()
688 next_id = (priv_state && priv_state->use_palette) ? HWDESC_PALETTE : plane_id; in ingenic_drm_plane_atomic_update()
690 hwdesc = &priv->dma_hwdescs->hwdesc[plane_id]; in ingenic_drm_plane_atomic_update()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c1010 int plane_id) in power_on_plane_resources() argument
1015 hws->funcs.dpp_root_clock_control(hws, plane_id, true); in power_on_plane_resources()
1022 hws->funcs.dpp_pg_control(hws, plane_id, true); in power_on_plane_resources()
1025 hws->funcs.hubp_pg_control(hws, plane_id, true); in power_on_plane_resources()
1030 "Un-gated front end for pipe %d\n", plane_id); in power_on_plane_resources()
/linux/tools/include/uapi/drm/
H A Di915_drm.h1926 __u32 plane_id; member
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c5359 struct amdgpu_mode_info *mode_info, int plane_id, in initialize_plane() argument
5380 possible_crtcs = 1 << plane_id; in initialize_plane()
5381 if (plane_id >= dm->dc->caps.max_streams) in initialize_plane()
5393 mode_info->planes[plane_id] = plane; in initialize_plane()