Searched refs:pl2 (Results 1 – 5 of 5) sorted by relevance
70 u32 pl2 = xe_gt_throttle_get_limit_reasons(gt) & POWER_LIMIT_2_MASK; in read_reason_pl2() local72 return pl2; in read_reason_pl2()144 bool pl2 = !!read_reason_pl2(gt); in reason_pl2_show() local146 return sysfs_emit(buff, "%u\n", pl2); in reason_pl2_show()
109 pl2_t pl2 = SET_PL2((unsigned long)*ptep | PDE_IDENT_ATTR); in init_map() local112 **pl2p = pl2; in init_map()115 *(*pl2p + ((PAGE_OFFSET >> PGDIR_SHIFT))) = pl2; in init_map()
161 u8 pl2; member1637 static int victus_s_set_cpu_pl1_pl2(u8 pl1, u8 pl2) in victus_s_set_cpu_pl1_pl2() argument1643 if (pl1 == HP_POWER_LIMIT_NO_CHANGE || pl2 == HP_POWER_LIMIT_NO_CHANGE) in victus_s_set_cpu_pl1_pl2()1647 if (pl2 < pl1) in victus_s_set_cpu_pl1_pl2()1651 power_limits.pl2 = pl2; in victus_s_set_cpu_pl1_pl2()
4707 const struct smu7_performance_level *pl2) in smu7_are_power_levels_equal() argument4709 return ((pl1->memory_clock == pl2->memory_clock) && in smu7_are_power_levels_equal()4710 (pl1->engine_clock == pl2->engine_clock) && in smu7_are_power_levels_equal()4711 (pl1->pcie_gen == pl2->pcie_gen) && in smu7_are_power_levels_equal()4712 (pl1->pcie_lane == pl2->pcie_lane)); in smu7_are_power_levels_equal()
5023 const struct vega10_performance_level *pl2) in vega10_are_power_levels_equal() argument5025 return ((pl1->soc_clock == pl2->soc_clock) && in vega10_are_power_levels_equal()5026 (pl1->gfx_clock == pl2->gfx_clock) && in vega10_are_power_levels_equal()5027 (pl1->mem_clock == pl2->mem_clock)); in vega10_are_power_levels_equal()