| /linux/drivers/media/i2c/ |
| H A D | ov02c10.c | 380 struct v4l2_ctrl *pixel_rate; member
495 s64 exposure_max, h_blank, pixel_rate; in ov02c10_init_controls() local
509 pixel_rate = div_u64(link_freq_menu_items[ov02c10->link_freq_index] * in ov02c10_init_controls()
512 ov02c10->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, in ov02c10_init_controls()
514 pixel_rate, 1, pixel_rate); in ov02c10_init_controls()
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| H A D | alvium-csi2.h | 360 struct v4l2_ctrl *pixel_rate; member
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| H A D | alvium-csi2.c | 2099 ctrls->pixel_rate = v4l2_ctrl_new_std(hdl, ops, in alvium_ctrl_init()
2103 ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY; in alvium_ctrl_init()
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| /linux/drivers/media/i2c/adv748x/ |
| H A D | adv748x-csi2.c | 293 if (!tx->pixel_rate) in adv748x_csi2_set_pixelrate()
296 return v4l2_ctrl_s_ctrl_int64(tx->pixel_rate, rate); in adv748x_csi2_set_pixelrate()
318 tx->pixel_rate = v4l2_ctrl_new_std(&tx->ctrl_hdl, in adv748x_csi2_init_controls()
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| /linux/drivers/gpu/drm/vc4/ |
| H A D | vc4_kms.c | 1006 unsigned long pixel_rate; in vc4_core_clock_atomic_check() local
1055 pixel_rate = load_state->hvs_load; in vc4_core_clock_atomic_check()
1057 pixel_rate = (pixel_rate * 40) / 100; in vc4_core_clock_atomic_check()
1059 pixel_rate = (pixel_rate * 60) / 100; in vc4_core_clock_atomic_check()
1062 hvs_new_state->core_clock_rate = max(cob_rate, pixel_rate); in vc4_core_clock_atomic_check()
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| /linux/drivers/gpu/drm/amd/display/dc/basics/ |
| H A D | dce_calcs.c | 268 data->pixel_rate[0] = data->pixel_rate[4]; in calculate_bandwidth()
269 data->pixel_rate[1] = data->pixel_rate[4]; in calculate_bandwidth()
271 data->pixel_rate[2] = data->pixel_rate[5]; in calculate_bandwidth()
272 data->pixel_rate[3] = data->pixel_rate[5]; in calculate_bandwidth()
399 data->pixel_rate[maximum_number_of_surfaces - 2] = data->pixel_rate[5]; in calculate_bandwidth()
400 data->pixel_rate[maximum_number_of_surfaces - 1] = data->pixel_rate[5]; in calculate_bandwidth()
853 …source_width_rounded_up_to_chunks[i]), (bw_div(data->h_total[i], data->pixel_rate[i]))), bw_int_to… in calculate_bandwidth()
1192 …i] = bw_div(bw_div(data->source_width_rounded_up_to_chunks[i], data->hsr[i]), data->pixel_rate[i]); in calculate_bandwidth()
1258 …pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_mul(data->dmif_burst_time… in calculate_bandwidth()
1298 …sor_dcp_buffer_lines, bw_int_to_fixed(1))), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]); in calculate_bandwidth()
[all …]
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| H A D | calcs_logger.h | 422 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pixel_rate[%d]:%d", i, bw_fixed_to_int(data->pixel_rate[i])); in print_bw_calcs_data()
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| /linux/drivers/gpu/drm/msm/dp/ |
| H A D | dp_ctrl.c | 2165 unsigned long pixel_rate; in msm_dp_ctrl_process_phy_test_request() local
2186 pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock; in msm_dp_ctrl_process_phy_test_request()
2187 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); in msm_dp_ctrl_process_phy_test_request()
2284 unsigned long pixel_rate; in msm_dp_ctrl_on_link() local
2292 pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock; in msm_dp_ctrl_on_link()
2299 if (!pixel_rate) in msm_dp_ctrl_on_link()
2300 pixel_rate = phy_cts_pixel_clk_khz; in msm_dp_ctrl_on_link()
2306 pixel_rate >>= 1; in msm_dp_ctrl_on_link()
2311 pixel_rate); in msm_dp_ctrl_on_link()
2480 unsigned long pixel_rate; in msm_dp_ctrl_on_stream() local
[all …]
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | skl_watermark.c | 654 crtc_state->pixel_rate, &wp, 0, 0); in skl_cursor_allocation()
1614 skl_wm_method1(struct intel_display *display, u32 pixel_rate, in skl_wm_method1() argument
1623 wm_intermediate_val = latency * pixel_rate * cpp; in skl_wm_method1()
1633 skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency, in skl_wm_method2() argument
1642 wm_intermediate_val = latency * pixel_rate; in skl_wm_method2()
1650 int pixel_rate) in skl_wm_linetime_us() argument
1653 pixel_rate); in skl_wm_linetime_us()
2165 int ret, pixel_rate, width, level = 0; in skl_wm0_prefill_lines_worst() local
2185 pixel_rate = DIV_ROUND_UP_ULL(mul_u32_u32(skl_scaler_max_total_scale(crtc_state), in skl_wm0_prefill_lines_worst()
2197 pixel_rate, &wp, 0, 1); in skl_wm0_prefill_lines_worst()
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| H A D | intel_display.c | 2192 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; in ilk_pipe_pixel_rate() local
2201 return pixel_rate; in ilk_pipe_pixel_rate()
2208 pixel_rate); in ilk_pipe_pixel_rate()
2238 crtc_state->pixel_rate = in intel_crtc_compute_pixel_rate()
2241 crtc_state->pixel_rate = in intel_crtc_compute_pixel_rate()
4222 crtc_state->pixel_rate); in skl_linetime_wm()
5358 PIPE_CONF_CHECK_I(pixel_rate); in intel_pipe_config_compare()
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| H A D | intel_cdclk.c | 2884 static int _intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state, int pixel_rate) in _intel_pixel_rate_to_cdclk() argument
2890 return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc); in _intel_pixel_rate_to_cdclk()
2895 return _intel_pixel_rate_to_cdclk(crtc_state, crtc_state->pixel_rate); in intel_pixel_rate_to_cdclk()
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| H A D | intel_plane.c | 242 crtc_state->pixel_rate); in intel_plane_pixel_rate()
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| H A D | intel_fbc.c | 1576 return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95); in _intel_fbc_min_cdclk()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | dce_calcs.h | 390 struct bw_fixed pixel_rate[maximum_number_of_surfaces]; member
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| /linux/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_vop2_reg.c | 781 .pixel_rate = 2,
791 .pixel_rate = 1,
799 .pixel_rate = 1,
1473 u8 port_pix_rate = vp->data->pixel_rate; in rk3576_set_intf_mux()
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