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Searched refs:pixel_clk (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi-qp.c218 unsigned long pixel_clk, in dw_hdmi_qp_match_tmds_n_table() argument
225 if (pixel_clk == common_tmds_n_table[i].tmds) { in dw_hdmi_qp_match_tmds_n_table()
251 unsigned int pixel_clk) in dw_hdmi_qp_audio_math_diff() argument
253 u64 cts = mul_u32_u32(pixel_clk, n); in dw_hdmi_qp_audio_math_diff()
259 unsigned long pixel_clk, in dw_hdmi_qp_compute_n() argument
271 if (dw_hdmi_qp_audio_math_diff(freq, ideal_n, pixel_clk) == 0) in dw_hdmi_qp_compute_n()
275 u64 diff = dw_hdmi_qp_audio_math_diff(freq, n, pixel_clk); in dw_hdmi_qp_compute_n()
295 static unsigned int dw_hdmi_qp_find_n(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk, in dw_hdmi_qp_find_n() argument
298 int n = dw_hdmi_qp_match_tmds_n_table(hdmi, pixel_clk, sample_rate); in dw_hdmi_qp_find_n()
304 pixel_clk); in dw_hdmi_qp_find_n()
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H A Ddw-mipi-dsi2.c325 u64 pixel_clk, ipi_clk, phy_hsclk; in dw_mipi_dsi2_phy_ratio_cfg() local
336 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; in dw_mipi_dsi2_phy_ratio_cfg()
337 ipi_clk = pixel_clk / 4; in dw_mipi_dsi2_phy_ratio_cfg()
457 u64 pixel_clk, phy_hs_clk; in dw_mipi_dsi2_ipi_set() local
478 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; in dw_mipi_dsi2_ipi_set()
483 hsa_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk); in dw_mipi_dsi2_ipi_set()
487 hbp_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk); in dw_mipi_dsi2_ipi_set()
491 hact_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk); in dw_mipi_dsi2_ipi_set()
495 hline_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk); in dw_mipi_dsi2_ipi_set()
/linux/drivers/media/platform/cadence/
H A Dcdns-csi2rx.c137 struct clk *pixel_clk[CSI2RX_STREAMS_MAX]; member
376 ret = clk_prepare_enable(csi2rx->pixel_clk[i]); in csi2rx_start()
417 clk_disable_unprepare(csi2rx->pixel_clk[i - 1]); in csi2rx_start()
456 clk_disable_unprepare(csi2rx->pixel_clk[i]); in csi2rx_stop()
748 csi2rx->pixel_clk[i] = devm_clk_get(&pdev->dev, name); in csi2rx_get_resources()
749 if (IS_ERR(csi2rx->pixel_clk[i])) { in csi2rx_get_resources()
751 return PTR_ERR(csi2rx->pixel_clk[i]); in csi2rx_get_resources()
H A Dcdns-csi2tx.c108 struct clk *pixel_clk[CSI2TX_STREAMS_MAX]; member
485 csi2tx->pixel_clk[i] = devm_clk_get(&pdev->dev, clk_name); in csi2tx_get_resources()
486 if (IS_ERR(csi2tx->pixel_clk[i])) { in csi2tx_get_resources()
489 return PTR_ERR(csi2tx->pixel_clk[i]); in csi2tx_get_resources()
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dpi.c75 struct clk *pixel_clk; member
512 clk_disable_unprepare(dpi->pixel_clk); in mtk_dpi_power_off()
536 ret = clk_prepare_enable(dpi->pixel_clk); in mtk_dpi_power_on()
592 clk_set_rate(dpi->pixel_clk, vm->pixelclock * 2); in mtk_dpi_set_pixel_clk()
594 clk_set_rate(dpi->pixel_clk, vm->pixelclock); in mtk_dpi_set_pixel_clk()
596 vm->pixelclock = clk_get_rate(dpi->pixel_clk); in mtk_dpi_set_pixel_clk()
1294 dpi->pixel_clk = devm_clk_get(dev, "pixel"); in mtk_dpi_probe()
1295 if (IS_ERR(dpi->pixel_clk)) in mtk_dpi_probe()
1296 return dev_err_probe(dev, PTR_ERR(dpi->pixel_clk), in mtk_dpi_probe()
/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_host.c119 struct clk *pixel_clk; member
336 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); in dsi_clk_init()
337 if (IS_ERR(msm_host->pixel_clk)) in dsi_clk_init()
338 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->pixel_clk), in dsi_clk_init()
396 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); in dsi_link_clk_set_rate_6g()
450 ret = clk_prepare_enable(msm_host->pixel_clk); in dsi_link_clk_enable_6g()
466 clk_disable_unprepare(msm_host->pixel_clk); in dsi_link_clk_enable_6g()
501 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); in dsi_link_clk_set_rate_v2()
532 ret = clk_prepare_enable(msm_host->pixel_clk); in dsi_link_clk_enable_v2()
555 clk_disable_unprepare(msm_host->pixel_clk); in dsi_link_clk_disable_6g()
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/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dclock_source.h180 unsigned int pixel_clk,
/linux/drivers/gpu/drm/msm/dp/
H A Ddp_ctrl.c130 struct clk *pixel_clk; member
2187 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); in msm_dp_ctrl_process_phy_test_request()
2196 ret = clk_prepare_enable(ctrl->pixel_clk); in msm_dp_ctrl_process_phy_test_request()
2509 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); in msm_dp_ctrl_on_stream()
2518 ret = clk_prepare_enable(ctrl->pixel_clk); in msm_dp_ctrl_on_stream()
2579 clk_disable_unprepare(ctrl->pixel_clk); in msm_dp_ctrl_off_link_stream()
2633 clk_disable_unprepare(ctrl->pixel_clk); in msm_dp_ctrl_off()
2737 ctrl->pixel_clk = devm_clk_get(dev, "stream_pixel"); in msm_dp_ctrl_clk_init()
2738 if (IS_ERR(ctrl->pixel_clk)) in msm_dp_ctrl_clk_init()
2739 return PTR_ERR(ctrl->pixel_clk); in msm_dp_ctrl_clk_init()
/linux/drivers/gpu/drm/aspeed/
H A Daspeed_gfx_crtc.c93 clk_set_rate(priv->pixel_clk, m->crtc_clock * 1000); in aspeed_gfx_crtc_mode_set_nofb()
/linux/drivers/gpu/drm/amd/display/dc/bios/
H A Dcommand_table.c1546 uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock; in adjust_display_pll_v2() local
1550 div_u64(pixel_clk * pixel_clk_10_khz_out, in adjust_display_pll_v2()
1596 uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock; in adjust_display_pll_v3() local
1600 div_u64(pixel_clk * pixel_clk_10_khz_out, in adjust_display_pll_v3()
H A Dbios_parser.c1323 info->lcd_timing.pixel_clk = in get_embedded_panel_info_v1_2()
1441 info->lcd_timing.pixel_clk = in get_embedded_panel_info_v1_3()
H A Dbios_parser2.c1456 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; in get_embedded_panel_info_v2_1()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c1307 unsigned int pixel_clk, in dcn20_override_dp_pix_clk() argument
1313 REG_WRITE(PHASE[inst], pixel_clk); in dcn20_override_dp_pix_clk()
/linux/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c699 u64 pixel_clk = 0; in vgpu_update_refresh_rate() local
704 pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n); in vgpu_update_refresh_rate()
705 pixel_clk *= MSEC_PER_SEC; in vgpu_update_refresh_rate()
708 …new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal… in vgpu_update_refresh_rate()