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Searched refs:pipe_plane (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
H A Ddml2_core_utils.h19 …ne_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane);
H A Ddml2_core_utils.c255 …ane_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane) in dml2_core_utils_pipe_plane_mapping() argument
260 pipe_plane[k] = __DML2_CALCS_PIPE_NO_PLANE__; in dml2_core_utils_pipe_plane_mapping()
265 pipe_plane[pipe_idx] = plane_idx; in dml2_core_utils_pipe_plane_mapping()
H A Ddml2_core_shared.c29 …ne_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane);
3011 …ane_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane) in dml_calc_pipe_plane_mapping() argument
3016 pipe_plane[k] = __DML2_CALCS_PIPE_NO_PLANE__; in dml_calc_pipe_plane_mapping()
3021 pipe_plane[pipe_idx] = plane_idx; in dml_calc_pipe_plane_mapping()
3041 unsigned int plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; in dml_get_is_phantom_pipe()
9836 dml_calc_pipe_plane_mapping(cfg_support_info, mode_lib->mp.pipe_plane); in dml2_core_shared_mode_programming()
9926 dml2_printf("DML::%s: pipe=%d is in plane=%d\n", __func__, k, mode_lib->mp.pipe_plane[k]); in dml2_core_shared_mode_programming()
11422 unsigned int plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; in dml_get_plane_idx()
11495 …dpte_group_bytes = (unsigned int)(mode_lib->mp.dpte_group_bytes[mode_lib->mp.pipe_plane[pipe_idx]]… in rq_dlg_get_rq_reg()
11496 mpte_group_bytes = (unsigned int)(mode_lib->mp.vm_group_bytes[mode_lib->mp.pipe_plane[pipe_idx]]); in rq_dlg_get_rq_reg()
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H A Ddml2_core_shared_types.h683 …unsigned int pipe_plane[DML2_MAX_PLANES]; // <brief used mainly by dv to map the pipe inst to plan… member
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddisplay_mode_util.c759 dml_uint_t plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; in dml_get_plane_idx()
771 if (plane_idx == mode_lib->mp.pipe_plane[i]) { in dml_get_pipe_idx()
782 void dml_calc_pipe_plane_mapping(const struct dml_hw_resource_st *hw, dml_uint_t *pipe_plane) in dml_calc_pipe_plane_mapping() argument
787 pipe_plane[k] = __DML_PIPE_NO_PLANE__; in dml_calc_pipe_plane_mapping()
792 pipe_plane[pipe_idx] = plane_idx; in dml_calc_pipe_plane_mapping()
H A Ddisplay_mode_util.h73 …oid dml_calc_pipe_plane_mapping(const struct dml_hw_resource_st *hw, dml_uint_t *pipe_plane);
H A Ddml2_mall_phantom.c257 …ckChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0)… in assign_subvp_pipe()
623 if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 && in dml2_svp_validate_static_schedulability()
H A Ddisplay_mode_core_structs.h1079 …dml_uint_t pipe_plane[__DML_NUM_PLANES__]; // <brief used mainly by dv to map the pipe inst to pla… member
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.c134 which_plane = mode_lib->vba.pipe_plane[which_pipe]; \
264 if (plane_idx == mode_lib->vba.pipe_plane[i]) { in get_pipe_idx()
282 plane_idx = mode_lib->vba.pipe_plane[pipe_idx]; in get_det_buffer_size_kbytes()
298 plane_idx = mode_lib->vba.pipe_plane[pipe_idx]; in get_is_phantom_pipe()
545 mode_lib->vba.pipe_plane[j] = mode_lib->vba.NumberOfActivePlanes; in fetch_pipe_params()
789 mode_lib->vba.pipe_plane[k] = in fetch_pipe_params()
H A Ddisplay_mode_vba.h589 unsigned int pipe_plane[DC__NUM_DPP__MAX]; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c520 num_dpp = vba->NoOfDPP[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]]; in dcn32_set_phantom_stream_timing()
521 phantom_vactive += num_dpp > 1 ? vba->meta_row_height[vba->pipe_plane[pipe_idx]] : 0; in dcn32_set_phantom_stream_timing()
634 …ckChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0 … in dcn32_assign_subvp_pipe()
635 …ckChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 && in dcn32_assign_subvp_pipe()
1063 …if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vlevel][vba->maxMpcComb][vba->pipe_plane[pipe_… in subvp_validate_static_schedulability()
1250 odm = vba->ODMCombineEnabled[vba->pipe_plane[dml_pipe_idx]] != in update_pipe_slice_table_with_split_flags()
1730 …lockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0) in dcn32_calculate_dlg_params()
2039 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled; in dcn32_apply_merge_split_flags_helper()
2222 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn32_internal_validate_bw()
3536 …ckChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0)… in dcn32_assign_fpo_vactive_candidate()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c830 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn21_fast_validate_bw()