Searched refs:pipe_offset (Results 1 – 9 of 9) sorted by relevance
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
H A D | dml2_core_dcn4.c | 257 …unsigned int stream_index, plane_index, pipe_offset, stream_already_populated_mask, main_plane_ind… in pack_mode_programming_params_with_implicit_subvp() local 328 …for (pipe_offset = 0; pipe_offset < programming->plane_programming[plane_index].num_dpps_required;… in pack_mode_programming_params_with_implicit_subvp() 330 …programming->plane_programming[plane_index].pipe_regs[pipe_offset] = &programming->pipe_regs[total… in pack_mode_programming_params_with_implicit_subvp() 331 …memset(programming->plane_programming[plane_index].pipe_regs[pipe_offset], 0, sizeof(struct dml2_d… in pack_mode_programming_params_with_implicit_subvp() 335 …_me_up.mode_lib, programming->plane_programming[plane_index].pipe_regs[pipe_offset], dml_internal_… in pack_mode_programming_params_with_implicit_subvp() 366 …for (pipe_offset = 0; pipe_offset < programming->plane_programming[main_plane_index].num_dpps_requ… in pack_mode_programming_params_with_implicit_subvp() 368 …programming->plane_programming[main_plane_index].phantom_plane.pipe_regs[pipe_offset] = &programmi… in pack_mode_programming_params_with_implicit_subvp() 369 …memset(programming->plane_programming[main_plane_index].phantom_plane.pipe_regs[pipe_offset], 0, s… in pack_mode_programming_params_with_implicit_subvp() 373 …ogramming->plane_programming[main_plane_index].phantom_plane.pipe_regs[pipe_offset], dml_internal_… in pack_mode_programming_params_with_implicit_subvp() 523 unsigned int pipe_offset; in core_dcn4_mode_programming() local [all …]
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/linux/drivers/gpu/drm/amd/display/dc/irq/dce110/ |
H A D | irq_service_dce110.c | 212 uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; in dce110_vblank_set() local 216 if (pipe_offset >= MAX_PIPES) in dce110_vblank_set() 219 tg = dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; in dce110_vblank_set()
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/linux/drivers/gpu/drm/radeon/ |
H A D | evergreen.c | 1832 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in evergreen_line_buffer_adjust() local 1873 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in evergreen_line_buffer_adjust() 1876 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in evergreen_line_buffer_adjust() 2168 u32 pipe_offset = radeon_crtc->crtc_id * 16; in evergreen_program_watermarks() local 2287 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks() 2291 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks() 2292 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks() 2296 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks() 2299 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks() 2300 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks() [all …]
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H A D | si.c | 1953 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce6_line_buffer_adjust() local 1983 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce6_line_buffer_adjust() 1986 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce6_line_buffer_adjust()
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H A D | cik.c | 8805 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce8_line_buffer_adjust() local 8837 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce8_line_buffer_adjust() 8840 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce8_line_buffer_adjust()
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/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | dce_v10_0.c | 599 u32 pipe_offset = amdgpu_crtc->crtc_id; in dce_v10_0_line_buffer_adjust() local 632 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v10_0_line_buffer_adjust() 634 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); in dce_v10_0_line_buffer_adjust() 637 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v10_0_line_buffer_adjust()
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H A D | dce_v11_0.c | 631 u32 pipe_offset = amdgpu_crtc->crtc_id; in dce_v11_0_line_buffer_adjust() local 664 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v11_0_line_buffer_adjust() 666 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); in dce_v11_0_line_buffer_adjust() 669 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v11_0_line_buffer_adjust()
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H A D | dce_v8_0.c | 554 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; in dce_v8_0_line_buffer_adjust() local 587 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce_v8_0_line_buffer_adjust() 590 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce_v8_0_line_buffer_adjust()
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H A D | dce_v6_0.c | 1015 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; in dce_v6_0_line_buffer_adjust() local 1045 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce_v6_0_line_buffer_adjust() 1048 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce_v6_0_line_buffer_adjust()
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