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Searched refs:pipe_offset (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/irq/dce110/
H A Dirq_service_dce110.c212 uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; in dce110_vblank_set() local
216 if (pipe_offset >= MAX_PIPES) in dce110_vblank_set()
219 tg = dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; in dce110_vblank_set()
/linux/drivers/gpu/drm/radeon/
H A Devergreen.c1832 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in evergreen_line_buffer_adjust() local
1873 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in evergreen_line_buffer_adjust()
1876 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in evergreen_line_buffer_adjust()
2168 u32 pipe_offset = radeon_crtc->crtc_id * 16; in evergreen_program_watermarks() local
2287 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks()
2291 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2292 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks()
2296 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks()
2299 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2300 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks()
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/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_device_queue_manager.c86 int pipe_offset = (mec * dqm->dev->kfd->shared_resources.num_pipe_per_mec in is_pipe_enabled() local
91 if (test_bit(pipe_offset + i, in is_pipe_enabled()
1527 int pipe_offset = pipe * get_queues_per_pipe(dqm); in initialize_nocpsch() local
1530 if (test_bit(pipe_offset + queue, in initialize_nocpsch()
3704 int pipe_offset = pipe * get_queues_per_pipe(dqm); in dqm_debugfs_hqds() local
3707 if (!test_bit(pipe_offset + queue, in dqm_debugfs_hqds()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v10_0.c599 u32 pipe_offset = amdgpu_crtc->crtc_id; in dce_v10_0_line_buffer_adjust() local
632 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v10_0_line_buffer_adjust()
634 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); in dce_v10_0_line_buffer_adjust()
637 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v10_0_line_buffer_adjust()
H A Ddce_v8_0.c554 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; in dce_v8_0_line_buffer_adjust() local
587 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce_v8_0_line_buffer_adjust()
590 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce_v8_0_line_buffer_adjust()
H A Ddce_v6_0.c1063 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; in dce_v6_0_line_buffer_adjust() local
1093 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce_v6_0_line_buffer_adjust()
1096 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce_v6_0_line_buffer_adjust()