| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | link_hwss.h | 38 struct pipe_ctx;
49 void (*set_hblank_min_symbol_width)(struct pipe_ctx *pipe_ctx,
52 void (*set_throttled_vcp_size)(struct pipe_ctx *pipe_ctx,
77 void (*setup_stream_encoder)(struct pipe_ctx *pipe_ctx);
78 void (*reset_stream_encoder)(struct pipe_ctx *pipe_ctx);
79 void (*setup_stream_attribute)(struct pipe_ctx *pipe_ctx);
83 void (*setup_audio_output)(struct pipe_ctx *pipe_ctx,
85 void (*enable_audio_packet)(struct pipe_ctx *pipe_ctx);
86 void (*disable_audio_packet)(struct pipe_ctx *pipe_ctx);
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| H A D | dce_calcs.h | 35 struct pipe_ctx;
484 const struct pipe_ctx *pipe,
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.h | 31 void dcn201_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);
33 void dcn201_unblank_stream(struct pipe_ctx *pipe_ctx,
35 void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
36 …d dcn201_plane_atomic_disconnect(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
37 void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
38 void dcn201_set_cursor_attribute(struct pipe_ctx *pipe_ctx);
41 struct pipe_ctx *pipe,
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_dc_resource_mgmt.c | 48 struct pipe_ctx *next_higher_pipe_for_odm_slice[MAX_PIPES];
52 struct pipe_ctx *prev_odm_pipe;
109 static struct pipe_ctx *find_master_pipe_of_stream(struct dml2_context *ctx, struct dc_state *state… in find_master_pipe_of_stream()
114 …if (state->res_ctx.pipe_ctx[i].stream && state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id… in find_master_pipe_of_stream()
115 if (!state->res_ctx.pipe_ctx[i].prev_odm_pipe && !state->res_ctx.pipe_ctx[i].top_pipe) in find_master_pipe_of_stream()
116 return &state->res_ctx.pipe_ctx[i]; in find_master_pipe_of_stream()
123 static struct pipe_ctx *find_master_pipe_of_plane(struct dml2_context *ctx, in find_master_pipe_of_plane()
130 …if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(ctx, state, state->res_ctx.pipe_ctx[i].… in find_master_pipe_of_plane()
131 state->res_ctx.pipe_ctx[i].stream->stream_id, in find_master_pipe_of_plane()
132 …ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pip… in find_master_pipe_of_plane()
[all …]
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| H A D | dml2_wrapper_fpu.c | 182 struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i]; in calculate_lowest_supported_state_for_temp_read()
290 struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i]; in dml_mode_support_wrapper()
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| /linux/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| H A D | link_hwss_virtual.h | 30 void virtual_setup_stream_encoder(struct pipe_ctx *pipe_ctx);
31 void virtual_setup_stream_attribute(struct pipe_ctx *pipe_ctx);
32 void virtual_reset_stream_encoder(struct pipe_ctx *pipe_ctx);
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| /linux/drivers/gpu/drm/amd/display/dc/basics/ |
| H A D | dc_common.h | 33 bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
35 bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
37 bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_hwss_hpo_frl.c | 29 static void setup_hpo_frl_stream_attribute(struct pipe_ctx *pipe_ctx) in setup_hpo_frl_stream_attribute() argument
31 struct hpo_frl_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_frl_stream_enc; in setup_hpo_frl_stream_attribute()
32 struct dc_stream_state *stream = pipe_ctx->stream; in setup_hpo_frl_stream_attribute()
33 struct pipe_ctx *odm_pipe; in setup_hpo_frl_stream_attribute()
37 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) in setup_hpo_frl_stream_attribute()
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| H A D | link_resource.c | 36 struct pipe_ctx *pipe = NULL; in link_get_cur_link_res()
41 pipe = &link->dc->current_state->res_ctx.pipe_ctx[i]; in link_get_cur_link_res()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_spl_translate.h | 15 void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_in *spl_in);
21 void translate_SPL_out_params_to_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_out *spl_out);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
| H A D | dcn314_hwseq.h | 34 void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
40 unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, un…
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| H A D | dce110_resource.h | 41 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 199 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn35_disable_otg_wa()
200 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; in dcn35_disable_otg_wa()
203 struct pipe_ctx *pipe = safe_to_lower in dcn35_disable_otg_wa()
204 ? &context->res_ctx.pipe_ctx[i] in dcn35_disable_otg_wa()
205 : &dc->current_state->res_ctx.pipe_ctx[i]; in dcn35_disable_otg_wa()
265 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn35_update_clocks_update_dtb_dto() local
269 if (pipe_ctx->stream_res.tg && in dcn35_update_clocks_update_dtb_dto()
270 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { in dcn35_update_clocks_update_dtb_dto()
271 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); in dcn35_update_clocks_update_dtb_dto()
273 dto_params.otg_inst = pipe_ctx->stream_res.tg->inst; in dcn35_update_clocks_update_dtb_dto()
[all …]
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_helpers.c | 1490 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; in dm_helpers_dp_handle_test_pattern_request()
1491 struct pipe_ctx *pipe_ctx = NULL; in dm_helpers_dp_handle_test_pattern_request() local
1504 pipe_ctx = &pipes[i]; in dm_helpers_dp_handle_test_pattern_request()
1509 if (pipe_ctx == NULL) in dm_helpers_dp_handle_test_pattern_request()
1570 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) in dm_helpers_dp_handle_test_pattern_request()
1572 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) { in dm_helpers_dp_handle_test_pattern_request()
1575 pipe_ctx->stream->timing.display_color_depth, in dm_helpers_dp_handle_test_pattern_request()
1576 pipe_ctx->stream->timing.pixel_encoding, in dm_helpers_dp_handle_test_pattern_request()
1579 pipe_ctx->stream->timing.display_color_depth = requestColorDepth; in dm_helpers_dp_handle_test_pattern_request()
1580 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding; in dm_helpers_dp_handle_test_pattern_request()
[all …]
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| H A D | amdgpu_dm.c | 4662 struct pipe_ctx *pipe = NULL; in dm_set_writeback()
4685 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) { in dm_set_writeback()
4686 pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i]; in dm_set_writeback()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce/ |
| H A D | dce_hwseq.c | 48 struct pipe_ctx *pipe, in dce_pipe_control_lock()
90 struct pipe_ctx *pipe, in dce60_pipe_control_lock()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| H A D | dce100_resource.c | 854 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); in build_mapped_resource() local
856 if (!pipe_ctx) in build_mapped_resource()
859 dce110_resource_build_pipe_hw_param(pipe_ctx); in build_mapped_resource()
861 resource_build_info_frame(pipe_ctx); in build_mapped_resource()
878 stream = context->res_ctx.pipe_ctx[i].stream; in dce100_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 158 struct pipe_ctx *pipe = safe_to_lower in dcn314_disable_otg_wa()
159 ? &context->res_ctx.pipe_ctx[i] in dcn314_disable_otg_wa()
160 : &dc->current_state->res_ctx.pipe_ctx[i]; in dcn314_disable_otg_wa()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.c | 123 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn31_disable_otg_wa()
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