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Searched refs:pipe_ctx (Results 1 – 25 of 54) sorted by relevance

123

/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.h34 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
36 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
43 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
44 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
45 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
47 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
50 struct pipe_ctx *pipe_ctx,
54 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx);
55 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
57 void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
[all …]
/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c152 struct pipe_ctx *pipes[MAX_PIPES]; in link_set_all_streams_dpms_off_for_link()
198 const struct pipe_ctx *pipe) in is_master_pipe_for_link()
211 struct pipe_ctx *pipes[MAX_PIPES]) in link_get_master_pipes_with_dpms_on()
214 struct pipe_ctx *pipe = NULL; in link_get_master_pipes_with_dpms_on()
218 pipe = &state->res_ctx.pipe_ctx[i]; in link_get_master_pipes_with_dpms_on()
526 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) in update_psp_stream_config() argument
528 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; in update_psp_stream_config()
529 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; in update_psp_stream_config()
532 dp_get_panel_mode(pipe_ctx->stream->link); in update_psp_stream_config()
536 if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) in update_psp_stream_config()
[all …]
H A Dlink_hwss_hpo_frl.c29 static void setup_hpo_frl_stream_attribute(struct pipe_ctx *pipe_ctx) in setup_hpo_frl_stream_attribute() argument
31 struct hpo_frl_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_frl_stream_enc; in setup_hpo_frl_stream_attribute()
32 struct dc_stream_state *stream = pipe_ctx->stream; in setup_hpo_frl_stream_attribute()
33 struct pipe_ctx *odm_pipe; in setup_hpo_frl_stream_attribute()
37 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) in setup_hpo_frl_stream_attribute()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c91 void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx) in dcn401_program_gamut_remap() argument
95 unsigned int mpcc_id = pipe_ctx->plane_res.mpcc_inst; in dcn401_program_gamut_remap()
96 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn401_program_gamut_remap()
103 if (pipe_ctx->plane_state && in dcn401_program_gamut_remap()
104 pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) { in dcn401_program_gamut_remap()
108 pipe_ctx->plane_state->gamut_remap_matrix.matrix[i]; in dcn401_program_gamut_remap()
124 if (pipe_ctx->top_pipe == NULL) { in dcn401_program_gamut_remap()
125 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { in dcn401_program_gamut_remap()
129 pipe_ctx->stream->gamut_remap_matrix.matrix[i]; in dcn401_program_gamut_remap()
377 void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx) in dcn401_trigger_3dlut_dma_load() argument
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c286 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, in dce110_set_input_transfer_func() argument
290 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; in dce110_set_input_transfer_func()
610 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, in dce110_set_output_transfer_func() argument
614 struct transform *xfm = pipe_ctx->plane_res.xfm; in dce110_set_output_transfer_func()
635 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) in dce110_update_info_frame() argument
640 ASSERT(pipe_ctx->stream); in dce110_update_info_frame()
642 if (pipe_ctx->stream_res.stream_enc == NULL) in dce110_update_info_frame()
645 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); in dce110_update_info_frame()
646 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); in dce110_update_info_frame()
652 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dce110_update_info_frame()
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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c708 const struct pipe_ctx *pipe_with_clk_src, in is_sharable_clk_src()
709 const struct pipe_ctx *pipe) in is_sharable_clk_src()
740 struct pipe_ctx *pipe_ctx) in resource_find_used_clk_src_for_sharing() argument
745 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) in resource_find_used_clk_src_for_sharing()
746 return res_ctx->pipe_ctx[i].clock_source; in resource_find_used_clk_src_for_sharing()
859 struct pipe_ctx *pipe_ctx, in calculate_plane_rec_in_timing_active() argument
923 const struct dc_stream_state *stream = pipe_ctx->stream; in calculate_plane_rec_in_timing_active()
949 struct pipe_ctx *pipe_ctx, in calculate_mpc_slice_in_timing_active() argument
952 const struct dc_stream_state *stream = pipe_ctx->stream; in calculate_mpc_slice_in_timing_active()
953 int mpc_slice_count = resource_get_mpc_slice_count(pipe_ctx); in calculate_mpc_slice_in_timing_active()
[all …]
H A Ddc_hw_sequencer.c319 struct pipe_ctx *pipe_ctx, in get_mpctree_visual_confirm_color() argument
331 struct pipe_ctx *top_pipe = pipe_ctx; in get_mpctree_visual_confirm_color()
340 const struct pipe_ctx *pipe_ctx, in get_surface_visual_confirm_color() argument
345 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color()
349 if (pipe_ctx->plane_state->layer_index > 0) { in get_surface_visual_confirm_color()
359 if (pipe_ctx->plane_state->layer_index > 0) { in get_surface_visual_confirm_color()
378 if (pipe_ctx->plane_state->layer_index > 0) { in get_surface_visual_confirm_color()
390 struct pipe_ctx *pipe_ctx, in get_hdr_visual_confirm_color() argument
397 struct pipe_ctx *top_pipe_ctx = pipe_ctx; in get_hdr_visual_confirm_color()
465 struct pipe_ctx *pipe_ctx, in get_vabc_visual_confirm_color() argument
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H A Ddc_stream.c268 struct pipe_ctx *pipe_to_program = NULL; in program_cursor_attributes()
277 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in program_cursor_attributes() local
279 if (pipe_ctx->stream != stream) in program_cursor_attributes()
283 pipe_to_program = pipe_ctx; in program_cursor_attributes()
286 dc->hwss.begin_cursor_offload_update(dc, pipe_ctx); in program_cursor_attributes()
294 dc->hwss.set_cursor_attribute(pipe_ctx); in program_cursor_attributes()
296 dc_send_update_cursor_info_to_dmu(pipe_ctx, i); in program_cursor_attributes()
298 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); in program_cursor_attributes()
300 dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx); in program_cursor_attributes()
415 struct pipe_ctx *pipe_to_program = NULL; in program_cursor_position()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c60 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) in patch_address_for_sbs_tb_stereo() argument
62 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
63 bool sec_split = pipe_ctx->top_pipe && in patch_address_for_sbs_tb_stereo()
64 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
67 (pipe_ctx->stream->timing.timing_3d_format == in patch_address_for_sbs_tb_stereo()
69 pipe_ctx->stream->timing.timing_3d_format == in patch_address_for_sbs_tb_stereo()
76 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && in patch_address_for_sbs_tb_stereo()
136 void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) in dcn201_update_plane_addr() argument
140 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in dcn201_update_plane_addr()
148 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); in dcn201_update_plane_addr()
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H A Ddcn201_hwseq.h31 void dcn201_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);
33 void dcn201_unblank_stream(struct pipe_ctx *pipe_ctx,
35 void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
36 …d dcn201_plane_atomic_disconnect(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
37 void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
38 void dcn201_set_cursor_attribute(struct pipe_ctx *pipe_ctx);
41 struct pipe_ctx *pipe,
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dlink_hwss.h38 struct pipe_ctx;
49 void (*set_hblank_min_symbol_width)(struct pipe_ctx *pipe_ctx,
52 void (*set_throttled_vcp_size)(struct pipe_ctx *pipe_ctx,
77 void (*setup_stream_encoder)(struct pipe_ctx *pipe_ctx);
78 void (*reset_stream_encoder)(struct pipe_ctx *pipe_ctx);
79 void (*setup_stream_attribute)(struct pipe_ctx *pipe_ctx);
83 void (*setup_audio_output)(struct pipe_ctx *pipe_ctx,
85 void (*enable_audio_packet)(struct pipe_ctx *pipe_ctx);
86 void (*disable_audio_packet)(struct pipe_ctx *pipe_ctx);
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/
H A Ddcn21_hwseq.c128 void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx) in dcn21_PLAT_58856_wa() argument
130 if (!pipe_ctx->stream->dpms_off) in dcn21_PLAT_58856_wa()
133 pipe_ctx->stream->dpms_off = false; in dcn21_PLAT_58856_wa()
134 pipe_ctx->stream->ctx->dc->link_srv->set_dpms_on(context, pipe_ctx); in dcn21_PLAT_58856_wa()
135 pipe_ctx->stream->ctx->dc->link_srv->set_dpms_off(pipe_ctx); in dcn21_PLAT_58856_wa()
136 pipe_ctx->stream->dpms_off = true; in dcn21_PLAT_58856_wa()
178 void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) in dcn21_set_abm_immediate_disable() argument
180 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_abm_immediate_disable()
181 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable()
182 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; in dcn21_set_abm_immediate_disable()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.h50 bool dcn32_set_mcm_luts(struct pipe_ctx *pipe_ctx,
54 struct pipe_ctx *pipe_ctx,
58 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream);
61 struct pipe_ctx *pipe_ctx,
72 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
74 void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
76 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, uns…
84 struct pipe_ctx *top_pipe_to_program,
89 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
92 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_utils.c156 bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx) in is_dp2p0_output_encoder() argument
158 if (pipe_ctx == NULL || pipe_ctx->stream == NULL) in is_dp2p0_output_encoder()
162 ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true); in is_dp2p0_output_encoder()
164 return (pipe_ctx->stream_res.hpo_dp_stream_enc && in is_dp2p0_output_encoder()
165 pipe_ctx->link_res.hpo_dp_link_enc && in is_dp2p0_output_encoder()
166 dc_is_dp_signal(pipe_ctx->stream->signal)); in is_dp2p0_output_encoder()
174 if (!context->res_ctx.pipe_ctx[i].stream) in is_dtbclk_required()
176 if (is_dp2p0_output_encoder(&context->res_ctx.pipe_ctx[i])) in is_dtbclk_required()
240 static void populate_pipe_ctx_dlg_params_from_dml(struct pipe_ctx *pipe_ctx, struct display_mode_li… in populate_pipe_ctx_dlg_params_from_dml() argument
243 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; in populate_pipe_ctx_dlg_params_from_dml()
[all …]
H A Ddml2_dc_resource_mgmt.c48 struct pipe_ctx *next_higher_pipe_for_odm_slice[MAX_PIPES];
52 struct pipe_ctx *prev_odm_pipe;
109 static struct pipe_ctx *find_master_pipe_of_stream(struct dml2_context *ctx, struct dc_state *state… in find_master_pipe_of_stream()
114 …if (state->res_ctx.pipe_ctx[i].stream && state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id… in find_master_pipe_of_stream()
115 if (!state->res_ctx.pipe_ctx[i].prev_odm_pipe && !state->res_ctx.pipe_ctx[i].top_pipe) in find_master_pipe_of_stream()
116 return &state->res_ctx.pipe_ctx[i]; in find_master_pipe_of_stream()
123 static struct pipe_ctx *find_master_pipe_of_plane(struct dml2_context *ctx, in find_master_pipe_of_plane()
130 …if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(ctx, state, state->res_ctx.pipe_ctx[i].… in find_master_pipe_of_plane()
131 state->res_ctx.pipe_ctx[i].stream->stream_id, in find_master_pipe_of_plane()
132 …ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pip… in find_master_pipe_of_plane()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_utils.c73 struct pipe_ctx *pipe, unsigned int *pipe_regs_idx) in find_pipe_regs_idx()
75 struct pipe_ctx *opp_head = dml_ctx->config.callbacks.get_opp_head(pipe); in find_pipe_regs_idx()
87 struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__], in dml21_find_dc_pipes_for_plane()
88 struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__], in dml21_find_dc_pipes_for_plane()
103 memset(dc_main_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__); in dml21_find_dc_pipes_for_plane()
104 memset(dc_phantom_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__); in dml21_find_dc_pipes_for_plane()
122 …struct pipe_ctx *otg_master_pipe = dml_ctx->config.callbacks.get_otg_master_for_stream(&context->r… in dml21_find_dc_pipes_for_plane()
148 struct pipe_ctx *pipe_ctx, in dml21_pipe_populate_global_sync() argument
153 if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) { in dml21_pipe_populate_global_sync()
158 memcpy(&pipe_ctx->global_sync, in dml21_pipe_populate_global_sync()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1252 struct pipe_ctx *pipe_ctx, in get_pixel_clock_parameters() argument
1255 const struct dc_stream_state *stream = pipe_ctx->stream; in get_pixel_clock_parameters()
1256 struct pipe_ctx *odm_pipe; in get_pixel_clock_parameters()
1259 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; in get_pixel_clock_parameters()
1260 struct dc *dc = pipe_ctx->stream->ctx->dc; in get_pixel_clock_parameters()
1263 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) in get_pixel_clock_parameters()
1273 pixel_clk_params->signal_type = pipe_ctx->stream->signal; in get_pixel_clock_parameters()
1274 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
1290 …else if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) || opp_cnt =… in get_pixel_clock_parameters()
1293 if (hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) in get_pixel_clock_parameters()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/link/hwss/
H A Dlink_hwss_virtual.h30 void virtual_setup_stream_encoder(struct pipe_ctx *pipe_ctx);
31 void virtual_setup_stream_attribute(struct pipe_ctx *pipe_ctx);
32 void virtual_reset_stream_encoder(struct pipe_ctx *pipe_ctx);
/linux/drivers/gpu/drm/amd/display/dc/basics/
H A Ddc_common.h33 bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
35 bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
37 bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c888 const struct pipe_ctx *pipe_ctx, in get_pixel_clock_parameters() argument
891 const struct dc_stream_state *stream = pipe_ctx->stream; in get_pixel_clock_parameters()
899 if (dc_is_rgb_signal(pipe_ctx->stream->signal)) in get_pixel_clock_parameters()
901 pixel_clk_params->signal_type = pipe_ctx->stream->signal; in get_pixel_clock_parameters()
902 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
924 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) in dce110_resource_build_pipe_hw_param() argument
926 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in dce110_resource_build_pipe_hw_param()
927 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( in dce110_resource_build_pipe_hw_param()
928 pipe_ctx->clock_source, in dce110_resource_build_pipe_hw_param()
929 &pipe_ctx->stream_res.pix_clk_params, in dce110_resource_build_pipe_hw_param()
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddmub_psr.c301 struct pipe_ctx *pipe_ctx = NULL; in dmub_psr_copy_settings() local
306 if (res_ctx->pipe_ctx[i].stream && in dmub_psr_copy_settings()
307 res_ctx->pipe_ctx[i].stream->link == link && in dmub_psr_copy_settings()
308 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { in dmub_psr_copy_settings()
309 pipe_ctx = &res_ctx->pipe_ctx[i]; in dmub_psr_copy_settings()
315 if (!pipe_ctx) in dmub_psr_copy_settings()
319 if (!dmub_psr_set_version(dmub, pipe_ctx->stream, panel_inst)) in dmub_psr_copy_settings()
341 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dmub_psr_copy_settings()
343 if (pipe_ctx->plane_res.dpp) in dmub_psr_copy_settings()
344 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; in dmub_psr_copy_settings()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_spl_translate.h15 void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_in *spl_in);
21 void translate_SPL_out_params_to_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_out *spl_out);
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c343 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_helper_populate_phantom_dlg_params()
468 struct pipe_ctx *ref_pipe, in dcn32_set_phantom_stream_timing()
475 struct pipe_ctx *pipe; in dcn32_set_phantom_stream_timing()
488 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_set_phantom_stream_timing()
565 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_get_num_free_pipes()
610 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_assign_subvp_pipe()
644 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_assign_subvp_pipe()
687 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_enough_pipes_for_subvp()
728 struct pipe_ctx *subvp_pipes[2] = {0}; in subvp_subvp_schedulable()
737 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in subvp_subvp_schedulable()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c998 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; in dcn20_populate_dml_writeback_from_context()
1000 if (!res_ctx->pipe_ctx[i].stream) in dcn20_populate_dml_writeback_from_context()
1042 …wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / … in dcn20_fpu_set_wb_arb_params()
1049 if (!context->res_ctx.pipe_ctx[i].stream) in is_dtbclk_required()
1051 if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i])) in is_dtbclk_required()
1064 if (context->res_ctx.pipe_ctx[i].plane_state) in decide_zstate_support()
1180 if (!context->res_ctx.pipe_ctx[i].stream) in dcn20_calculate_dlg_params()
1182 if (context->res_ctx.pipe_ctx[i].plane_state) in dcn20_calculate_dlg_params()
1189 if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) { in dcn20_calculate_dlg_params()
1191 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0; in dcn20_calculate_dlg_params()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
H A Ddcn314_hwseq.h34 void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
40 unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, un…

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