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Searched refs:pipe_ctx (Results 1 – 25 of 39) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn50/
H A Ddcn50_hwseq.c85 struct pipe_ctx *pipe_ctx, in dcn50_update_dchubp_dpp() argument
89 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn50_update_dchubp_dpp()
90 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn50_update_dchubp_dpp()
91 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in dcn50_update_dchubp_dpp()
94 enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe_ctx); in dcn50_update_dchubp_dpp()
96 if (pipe_ctx->update_flags.bits.dppclk) in dcn50_update_dchubp_dpp()
99 if (pipe_ctx->update_flags.bits.enable) in dcn50_update_dchubp_dpp()
100 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); in dcn50_update_dchubp_dpp()
107 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { in dcn50_update_dchubp_dpp()
108 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); in dcn50_update_dchubp_dpp()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c742 const struct pipe_ctx *pipe_with_clk_src, in is_sharable_clk_src()
743 const struct pipe_ctx *pipe) in is_sharable_clk_src()
774 struct pipe_ctx *pipe_ctx) in resource_find_used_clk_src_for_sharing() argument
779 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) in resource_find_used_clk_src_for_sharing()
780 return res_ctx->pipe_ctx[i].clock_source; in resource_find_used_clk_src_for_sharing()
923 struct pipe_ctx *pipe_ctx, in calculate_plane_rec_in_timing_active() argument
987 const struct dc_stream_state *stream = pipe_ctx->stream; in calculate_plane_rec_in_timing_active()
1013 struct pipe_ctx *pipe_ctx, in calculate_mpc_slice_in_timing_active() argument
1016 const struct dc_stream_state *stream = pipe_ctx->stream; in calculate_mpc_slice_in_timing_active()
1017 int mpc_slice_count = resource_get_mpc_slice_count(pipe_ctx); in calculate_mpc_slice_in_timing_active()
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H A Ddc_surface.c74 struct pipe_ctx *pipe_ctx = &dc_state->res_ctx.pipe_ctx[i]; in dc_plane_get_pipe_mask() local
76 if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp) in dc_plane_get_pipe_mask()
77 pipe_mask |= (uint8_t)(1 << pipe_ctx->plane_res.hubp->inst); in dc_plane_get_pipe_mask()
134 struct pipe_ctx *pipe_ctx = in dc_plane_get_status() local
135 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()
137 if (pipe_ctx->plane_state != plane_state) in dc_plane_get_status()
140 if (pipe_ctx->plane_state && flags.bits.address) in dc_plane_get_status()
141 pipe_ctx->plane_state->status.is_flip_pending = false; in dc_plane_get_status()
142 if (pipe_ctx->plane_state && flags.bits.histogram) in dc_plane_get_status()
143 memset(&pipe_ctx->plane_state->status.cm_hist, 0, in dc_plane_get_status()
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H A Ddc.c434 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in set_long_vtotal()
471 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_last_used_drr_vtotal()
532 struct pipe_ctx *pipe; in dc_stream_forward_crc_window()
537 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_forward_crc_window()
598 struct pipe_ctx *pipe; in dc_stream_forward_multiple_crc_window()
603 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_forward_multiple_crc_window()
648 struct pipe_ctx *pipe; in dc_stream_configure_crc()
722 struct pipe_ctx *pipe = NULL; in dc_stream_get_crc()
728 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_crc()
749 struct pipe_ctx *pipe_ctx; in dc_stream_set_dyn_expansion() local
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn60/
H A Ddcn60_hwseq.c57 const struct pipe_ctx *pipe_ctx, in dcn60_build_audio_output() argument
60 const struct dc_stream_state *stream = pipe_ctx->stream; in dcn60_build_audio_output()
61 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; in dcn60_build_audio_output()
63 audio_output->signal = pipe_ctx->stream->signal; in dcn60_build_audio_output()
97 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; in dcn60_build_audio_output()
100 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; in dcn60_build_audio_output()
112 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && in dcn60_build_audio_output()
115 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { in dcn60_build_audio_output()
119 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2; in dcn60_build_audio_output()
123 if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_FRL) { in dcn60_build_audio_output()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dlink_hwss.h38 struct pipe_ctx;
49 void (*set_hblank_min_symbol_width)(struct pipe_ctx *pipe_ctx,
52 void (*set_throttled_vcp_size)(struct pipe_ctx *pipe_ctx,
77 void (*setup_stream_encoder)(struct pipe_ctx *pipe_ctx);
78 void (*reset_stream_encoder)(struct pipe_ctx *pipe_ctx);
79 void (*setup_stream_attribute)(struct pipe_ctx *pipe_ctx);
83 void (*setup_audio_output)(struct pipe_ctx *pipe_ctx,
85 void (*enable_audio_packet)(struct pipe_ctx *pipe_ctx);
86 void (*disable_audio_packet)(struct pipe_ctx *pipe_ctx);
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.h31 void dcn201_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);
33 void dcn201_unblank_stream(struct pipe_ctx *pipe_ctx,
35 void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
36 …d dcn201_plane_atomic_disconnect(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
37 void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
38 void dcn201_set_cursor_attribute(struct pipe_ctx *pipe_ctx);
41 struct pipe_ctx *pipe,
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_dc_resource_mgmt.c48 struct pipe_ctx *next_higher_pipe_for_odm_slice[MAX_PIPES];
52 struct pipe_ctx *prev_odm_pipe;
109 static struct pipe_ctx *find_master_pipe_of_stream(struct dml2_context *ctx, struct dc_state *state… in find_master_pipe_of_stream()
114 …if (state->res_ctx.pipe_ctx[i].stream && state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id… in find_master_pipe_of_stream()
115 if (!state->res_ctx.pipe_ctx[i].prev_odm_pipe && !state->res_ctx.pipe_ctx[i].top_pipe) in find_master_pipe_of_stream()
116 return &state->res_ctx.pipe_ctx[i]; in find_master_pipe_of_stream()
123 static struct pipe_ctx *find_master_pipe_of_plane(struct dml2_context *ctx, in find_master_pipe_of_plane()
130 …if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(ctx, state, state->res_ctx.pipe_ctx[i].… in find_master_pipe_of_plane()
131 state->res_ctx.pipe_ctx[i].stream->stream_id, in find_master_pipe_of_plane()
132 …ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pip… in find_master_pipe_of_plane()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c237 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) in dcn30_set_blend_lut() argument
239 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut()
318 struct pipe_ctx *pipe_ctx, in dcn30_set_input_transfer_func() argument
322 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_input_transfer_func()
347 if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) { in dcn30_set_input_transfer_func()
349 hws->funcs.set_blend_lut(pipe_ctx, plane_state); in dcn30_set_input_transfer_func()
352 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); in dcn30_set_input_transfer_func()
615 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe]; in dcn30_program_all_writeback_pipes_in_tree() local
617 if (!pipe_ctx->plane_state) in dcn30_program_all_writeback_pipes_in_tree()
620 if (pipe_ctx->plane_state == wb_info.writeback_source_plane) { in dcn30_program_all_writeback_pipes_in_tree()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/link/hwss/
H A Dlink_hwss_virtual.h30 void virtual_setup_stream_encoder(struct pipe_ctx *pipe_ctx);
31 void virtual_setup_stream_attribute(struct pipe_ctx *pipe_ctx);
32 void virtual_reset_stream_encoder(struct pipe_ctx *pipe_ctx);
/linux/drivers/gpu/drm/amd/display/dc/basics/
H A Ddc_common.h33 bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
35 bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
37 bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_hwss_hpo_frl.c29 static void setup_hpo_frl_stream_attribute(struct pipe_ctx *pipe_ctx) in setup_hpo_frl_stream_attribute() argument
31 struct hpo_frl_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_frl_stream_enc; in setup_hpo_frl_stream_attribute()
32 struct dc_stream_state *stream = pipe_ctx->stream; in setup_hpo_frl_stream_attribute()
33 struct pipe_ctx *odm_pipe; in setup_hpo_frl_stream_attribute()
37 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) in setup_hpo_frl_stream_attribute()
H A Dlink_resource.c36 struct pipe_ctx *pipe = NULL; in link_get_cur_link_res()
41 pipe = &link->dc->current_state->res_ctx.pipe_ctx[i]; in link_get_cur_link_res()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_debugfs.c1294 struct pipe_ctx *pipe_ctx = NULL; in odm_combine_segments_show() local
1298 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; in odm_combine_segments_show()
1299 if (pipe_ctx->stream && in odm_combine_segments_show()
1300 pipe_ctx->stream->link == link) in odm_combine_segments_show()
1307 if (pipe_ctx && pipe_ctx->stream_res.tg && in odm_combine_segments_show()
1308 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments) in odm_combine_segments_show()
1309 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments); in odm_combine_segments_show()
1569 struct pipe_ctx *pipe_ctx; in dp_dsc_clock_en_read() local
1579 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; in dp_dsc_clock_en_read()
1580 if (pipe_ctx->stream && in dp_dsc_clock_en_read()
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H A Damdgpu_dm_helpers.c1493 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; in dm_helpers_dp_handle_test_pattern_request()
1494 struct pipe_ctx *pipe_ctx = NULL; in dm_helpers_dp_handle_test_pattern_request() local
1507 pipe_ctx = &pipes[i]; in dm_helpers_dp_handle_test_pattern_request()
1512 if (pipe_ctx == NULL) in dm_helpers_dp_handle_test_pattern_request()
1573 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) in dm_helpers_dp_handle_test_pattern_request()
1575 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) { in dm_helpers_dp_handle_test_pattern_request()
1578 pipe_ctx->stream->timing.display_color_depth, in dm_helpers_dp_handle_test_pattern_request()
1579 pipe_ctx->stream->timing.pixel_encoding, in dm_helpers_dp_handle_test_pattern_request()
1582 pipe_ctx->stream->timing.display_color_depth = requestColorDepth; in dm_helpers_dp_handle_test_pattern_request()
1583 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding; in dm_helpers_dp_handle_test_pattern_request()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_spl_translate.h15 void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_in *spl_in);
21 void translate_SPL_out_params_to_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_out *spl_out);
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
H A Ddcn314_hwseq.h34 void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
40 unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, un…
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn60/
H A Ddcn60_resource.c883 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; in build_mcache_pipe_regs_config() local
884 if (get_plane_index(context, pipe_ctx->plane_state, &plane_idx) && pipe_ctx->plane_res.hubp) { in build_mcache_pipe_regs_config()
885 reset_mcache_allocations(&pipe_ctx->mcache_regs); in build_mcache_pipe_regs_config()
886 if (pipe_ctx->plane_state->dcc.enable) { in build_mcache_pipe_regs_config()
891 pipe_ctx->plane_res.scl_data.viewport.x, in build_mcache_pipe_regs_config()
892 pipe_ctx->plane_res.scl_data.viewport.x + in build_mcache_pipe_regs_config()
893 pipe_ctx->plane_res.scl_data.viewport.width - 1, in build_mcache_pipe_regs_config()
899 pipe_ctx->mcache_regs.main.p0.mcache_id_first = in build_mcache_pipe_regs_config()
902 pipe_ctx->mcache_regs.mall.p0.mcache_id_first = in build_mcache_pipe_regs_config()
906 pipe_ctx->mcache_regs.main.p0.mcache_id_second = in build_mcache_pipe_regs_config()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c1816 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; in dcn32_enable_phantom_plane()
1861 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; in dcn32_enable_phantom_stream()
1900 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_add_phantom_pipes()
2044 struct pipe_ctx *pipe = NULL; in dcn32_populate_dml_pipes_from_context()
2076 pipe = &res_ctx->pipe_ctx[i]; in dcn32_populate_dml_pipes_from_context()
2077 if (!res_ctx->pipe_ctx[i].stream) in dcn32_populate_dml_pipes_from_context()
2091 if (!res_ctx->pipe_ctx[i].stream) in dcn32_populate_dml_pipes_from_context()
2093 pipe = &res_ctx->pipe_ctx[i]; in dcn32_populate_dml_pipes_from_context()
2112 odm_slice_count = resource_get_odm_slice_count(&res_ctx->pipe_ctx[subvp_main_pipe_index]); in dcn32_populate_dml_pipes_from_context()
2817 const struct pipe_ctx *new_opp_head) in dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c199 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn35_disable_otg_wa()
200 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; in dcn35_disable_otg_wa()
203 struct pipe_ctx *pipe = safe_to_lower in dcn35_disable_otg_wa()
204 ? &context->res_ctx.pipe_ctx[i] in dcn35_disable_otg_wa()
205 : &dc->current_state->res_ctx.pipe_ctx[i]; in dcn35_disable_otg_wa()
265 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn35_update_clocks_update_dtb_dto() local
269 if (pipe_ctx->stream_res.tg && in dcn35_update_clocks_update_dtb_dto()
270 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { in dcn35_update_clocks_update_dtb_dto()
271 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); in dcn35_update_clocks_update_dtb_dto()
273 dto_params.otg_inst = pipe_ctx->stream_res.tg->inst; in dcn35_update_clocks_update_dtb_dto()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.h41 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx);
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1492 if (!res_ctx->pipe_ctx[i].stream) in dcn30_populate_dml_pipes_from_context()
1549 if (!context->res_ctx.pipe_ctx[i].stream) in dcn30_set_mcif_arb_params()
1553 …struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j]; in dcn30_set_mcif_arb_params()
1570 …wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;… in dcn30_set_mcif_arb_params()
1684 struct pipe_ctx *pri_pipe, in dcn30_split_stream_for_mpc_or_odm()
1685 struct pipe_ctx *sec_pipe, in dcn30_split_stream_for_mpc_or_odm()
1743 static struct pipe_ctx *dcn30_find_split_pipe( in dcn30_find_split_pipe()
1748 struct pipe_ctx *pipe = NULL; in dcn30_find_split_pipe()
1751 if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) { in dcn30_find_split_pipe()
1752 pipe = &context->res_ctx.pipe_ctx[old_index]; in dcn30_find_split_pipe()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/
H A Ddcn60_clk_mgr.c167 static bool dcn60_check_native_scaling(struct pipe_ctx *pipe) in dcn60_check_native_scaling()
191 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn60_update_clocks_update_dpp_dto()
193 if (context->res_ctx.pipe_ctx[i].plane_res.dpp) in dcn60_update_clocks_update_dpp_dto()
194 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; in dcn60_update_clocks_update_dpp_dto()
195 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) { in dcn60_update_clocks_update_dpp_dto()
200 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) { in dcn60_update_clocks_update_dpp_dto()
248 struct pipe_ctx *otg_master; in dcn60_update_clocks_update_dtb_dto()
294 struct pipe_ctx *otg_master; in dcn60_build_update_display_clocks_sequence()
836 struct pipe_ctx *pipe_ctx_list[MAX_PIPES]; in dcn60_auto_dpm_test_log()
840 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn60_auto_dpm_test_log() local
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c1808 if (!res_ctx->pipe_ctx[i].stream) in allow_pixel_rate_crb()
1812 if (res_ctx->pipe_ctx[i].stream->src.width != res_ctx->pipe_ctx[i].stream->dst.width || in allow_pixel_rate_crb()
1813 res_ctx->pipe_ctx[i].stream->src.height != res_ctx->pipe_ctx[i].stream->dst.height || in allow_pixel_rate_crb()
1814 (res_ctx->pipe_ctx[i].plane_state && (res_ctx->pipe_ctx[i].plane_state->src_rect.width in allow_pixel_rate_crb()
1815 != res_ctx->pipe_ctx[i].plane_state->dst_rect.width || in allow_pixel_rate_crb()
1816 res_ctx->pipe_ctx[i].plane_state->src_rect.height in allow_pixel_rate_crb()
1817 != res_ctx->pipe_ctx[i].plane_state->dst_rect.height))) in allow_pixel_rate_crb()
1820 …if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_c… in allow_pixel_rate_crb()
1834 struct pipe_ctx *pipe = NULL; in dcn315_populate_dml_pipes_from_context()
1846 if (!res_ctx->pipe_ctx[i].stream) in dcn315_populate_dml_pipes_from_context()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.c48 struct pipe_ctx *pipe, in dce_pipe_control_lock()
90 struct pipe_ctx *pipe, in dce60_pipe_control_lock()

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