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Searched refs:phydev (Results 1 – 25 of 193) sorted by relevance

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/linux/drivers/net/phy/
H A Dphy-c45.c19 static bool genphy_c45_baset1_able(struct phy_device *phydev) in genphy_c45_baset1_able() argument
23 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able()
24 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); in genphy_c45_baset1_able()
28 phydev->pma_extable = val; in genphy_c45_baset1_able()
31 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able()
38 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev) in genphy_c45_pma_can_sleep() argument
42 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1); in genphy_c45_pma_can_sleep()
53 int genphy_c45_pma_resume(struct phy_device *phydev) in genphy_c45_pma_resume() argument
55 if (!genphy_c45_pma_can_sleep(phydev)) in genphy_c45_pma_resume()
58 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_resume()
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H A Dphy_device.c57 int (*run)(struct phy_device *phydev);
210 void phy_device_free(struct phy_device *phydev) in phy_device_free() argument
212 put_device(&phydev->mdio.dev); in phy_device_free()
218 struct phy_device *phydev; in phy_mdio_device_free() local
220 phydev = container_of(mdiodev, struct phy_device, mdio); in phy_mdio_device_free()
221 phy_device_free(phydev); in phy_mdio_device_free()
232 struct phy_device *phydev; in phy_mdio_device_remove() local
234 phydev = container_of(mdiodev, struct phy_device, mdio); in phy_mdio_device_remove()
235 phy_device_remove(phydev); in phy_mdio_device_remove()
243 static bool phy_drv_wol_enabled(struct phy_device *phydev) in phy_drv_wol_enabled() argument
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H A Dbroadcom.c26 #define BRCM_PHY_REV(phydev) \ argument
27 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
63 static bool bcm54xx_phy_can_wakeup(struct phy_device *phydev) in bcm54xx_phy_can_wakeup() argument
65 struct bcm54xx_phy_priv *priv = phydev->priv; in bcm54xx_phy_can_wakeup()
67 return phy_interrupt_is_valid(phydev) || priv->wake_irq >= 0; in bcm54xx_phy_can_wakeup()
70 static int bcm54xx_config_clock_delay(struct phy_device *phydev) in bcm54xx_config_clock_delay() argument
75 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); in bcm54xx_config_clock_delay()
77 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || in bcm54xx_config_clock_delay()
78 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in bcm54xx_config_clock_delay()
82 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in bcm54xx_config_clock_delay()
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H A Dbcm7xxx.c50 static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_d0_afe_config_init() argument
53 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15); in bcm7xxx_28nm_d0_afe_config_init()
56 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); in bcm7xxx_28nm_d0_afe_config_init()
59 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003); in bcm7xxx_28nm_d0_afe_config_init()
62 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0); in bcm7xxx_28nm_d0_afe_config_init()
65 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); in bcm7xxx_28nm_d0_afe_config_init()
68 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); in bcm7xxx_28nm_d0_afe_config_init()
71 bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020); in bcm7xxx_28nm_d0_afe_config_init()
76 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); in bcm7xxx_28nm_d0_afe_config_init()
79 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
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H A Dbcm-phy-lib.c21 int __bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val) in __bcm_phy_write_exp() argument
25 rc = __phy_write(phydev, MII_BCM54XX_EXP_SEL, reg); in __bcm_phy_write_exp()
29 return __phy_write(phydev, MII_BCM54XX_EXP_DATA, val); in __bcm_phy_write_exp()
33 int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val) in bcm_phy_write_exp() argument
37 phy_lock_mdio_bus(phydev); in bcm_phy_write_exp()
38 rc = __bcm_phy_write_exp(phydev, reg, val); in bcm_phy_write_exp()
39 phy_unlock_mdio_bus(phydev); in bcm_phy_write_exp()
45 int __bcm_phy_read_exp(struct phy_device *phydev, u16 reg) in __bcm_phy_read_exp() argument
49 val = __phy_write(phydev, MII_BCM54XX_EXP_SEL, reg); in __bcm_phy_read_exp()
53 val = __phy_read(phydev, MII_BCM54XX_EXP_DATA); in __bcm_phy_read_exp()
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H A Dmarvell-88q2xxx.c220 static int mv88q2xxx_write_mmd_vals(struct phy_device *phydev, in mv88q2xxx_write_mmd_vals() argument
226 ret = phy_write_mmd(phydev, vals->devad, vals->regnum, in mv88q2xxx_write_mmd_vals()
235 static int mv88q2xxx_soft_reset(struct phy_device *phydev) in mv88q2xxx_soft_reset() argument
241 if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed == SPEED_1000) { in mv88q2xxx_soft_reset()
242 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe1b, 0x48); in mv88q2xxx_soft_reset()
247 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_1000BT1_CTRL, in mv88q2xxx_soft_reset()
252 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS, in mv88q2xxx_soft_reset()
259 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xffe4, 0xc); in mv88q2xxx_soft_reset()
264 if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed == SPEED_1000) in mv88q2xxx_soft_reset()
265 return phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe1b, 0x58); in mv88q2xxx_soft_reset()
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H A Dmotorcomm.c406 static int ytphy_read_ext(struct phy_device *phydev, u16 regnum) in ytphy_read_ext() argument
410 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); in ytphy_read_ext()
414 return __phy_read(phydev, YTPHY_PAGE_DATA); in ytphy_read_ext()
424 static int ytphy_read_ext_with_lock(struct phy_device *phydev, u16 regnum) in ytphy_read_ext_with_lock() argument
428 phy_lock_mdio_bus(phydev); in ytphy_read_ext_with_lock()
429 ret = ytphy_read_ext(phydev, regnum); in ytphy_read_ext_with_lock()
430 phy_unlock_mdio_bus(phydev); in ytphy_read_ext_with_lock()
445 static int ytphy_write_ext(struct phy_device *phydev, u16 regnum, u16 val) in ytphy_write_ext() argument
449 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); in ytphy_write_ext()
453 return __phy_write(phydev, YTPHY_PAGE_DATA, val); in ytphy_write_ext()
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H A Dmicrel.c415 struct phy_device *phydev; member
433 struct phy_device *phydev; member
554 static int kszphy_extended_write(struct phy_device *phydev, in kszphy_extended_write() argument
557 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); in kszphy_extended_write()
558 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); in kszphy_extended_write()
561 static int kszphy_extended_read(struct phy_device *phydev, in kszphy_extended_read() argument
564 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); in kszphy_extended_read()
565 return phy_read(phydev, MII_KSZPHY_EXTREG_READ); in kszphy_extended_read()
568 static int kszphy_ack_interrupt(struct phy_device *phydev) in kszphy_ack_interrupt() argument
573 rc = phy_read(phydev, MII_KSZPHY_INTCS); in kszphy_ack_interrupt()
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H A Dmarvell.c359 static int marvell_read_page(struct phy_device *phydev) in marvell_read_page() argument
361 return __phy_read(phydev, MII_MARVELL_PHY_PAGE); in marvell_read_page()
364 static int marvell_write_page(struct phy_device *phydev, int page) in marvell_write_page() argument
366 return __phy_write(phydev, MII_MARVELL_PHY_PAGE, page); in marvell_write_page()
369 static int marvell_set_page(struct phy_device *phydev, int page) in marvell_set_page() argument
371 return phy_write(phydev, MII_MARVELL_PHY_PAGE, page); in marvell_set_page()
374 static int marvell_ack_interrupt(struct phy_device *phydev) in marvell_ack_interrupt() argument
379 err = phy_read(phydev, MII_M1011_IEVENT); in marvell_ack_interrupt()
387 static int marvell_config_intr(struct phy_device *phydev) in marvell_config_intr() argument
391 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in marvell_config_intr()
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H A Dair_en8811h.c202 struct phy_device *phydev; member
273 static int __air_write_buf(struct phy_device *phydev, u32 address, in __air_write_buf() argument
280 ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_INCR); in __air_write_buf()
284 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH, in __air_write_buf()
289 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW, in __air_write_buf()
296 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, val); in __air_write_buf()
301 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, val); in __air_write_buf()
309 static int air_write_buf(struct phy_device *phydev, u32 address, in air_write_buf() argument
315 saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); in air_write_buf()
318 ret = __air_write_buf(phydev, address, fw); in air_write_buf()
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H A Ddp83869.c157 static int dp83869_config_aneg(struct phy_device *phydev) in dp83869_config_aneg() argument
159 struct dp83869_private *dp83869 = phydev->priv; in dp83869_config_aneg()
162 return genphy_config_aneg(phydev); in dp83869_config_aneg()
164 return genphy_c37_config_aneg(phydev); in dp83869_config_aneg()
167 static int dp83869_read_status(struct phy_device *phydev) in dp83869_read_status() argument
169 struct dp83869_private *dp83869 = phydev->priv; in dp83869_read_status()
174 return genphy_c37_read_status(phydev, &changed); in dp83869_read_status()
176 ret = genphy_read_status(phydev); in dp83869_read_status()
181 if (phydev->link) { in dp83869_read_status()
182 phydev->speed = SPEED_100; in dp83869_read_status()
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H A Dbcm-phy-lib.h33 int __bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val);
34 int __bcm_phy_read_exp(struct phy_device *phydev, u16 reg);
35 int __bcm_phy_modify_exp(struct phy_device *phydev, u16 reg, u16 mask, u16 set);
36 int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val);
37 int bcm_phy_read_exp(struct phy_device *phydev, u16 reg);
38 int bcm_phy_modify_exp(struct phy_device *phydev, u16 reg, u16 mask, u16 set);
40 static inline int bcm_phy_write_exp_sel(struct phy_device *phydev, in bcm_phy_write_exp_sel() argument
43 return bcm_phy_write_exp(phydev, reg | MII_BCM54XX_EXP_SEL_ER, val); in bcm_phy_write_exp_sel()
46 static inline int bcm_phy_read_exp_sel(struct phy_device *phydev, u16 reg) in bcm_phy_read_exp_sel() argument
48 return bcm_phy_read_exp(phydev, reg | MII_BCM54XX_EXP_SEL_ER); in bcm_phy_read_exp_sel()
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H A Dnxp-tja11xx.c90 struct phy_device *phydev; member
111 static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set) in tja11xx_check() argument
115 return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set, in tja11xx_check()
119 static int phy_modify_check(struct phy_device *phydev, u8 reg, in phy_modify_check() argument
124 ret = phy_modify(phydev, reg, mask, set); in phy_modify_check()
128 return tja11xx_check(phydev, reg, mask, set); in phy_modify_check()
131 static int tja11xx_enable_reg_write(struct phy_device *phydev) in tja11xx_enable_reg_write() argument
133 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN); in tja11xx_enable_reg_write()
136 static int tja11xx_enable_link_control(struct phy_device *phydev) in tja11xx_enable_link_control() argument
138 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL); in tja11xx_enable_link_control()
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H A Dmicrochip_t1.c334 static int lan937x_dsp_workaround(struct phy_device *phydev, u16 ereg, u8 bank) in lan937x_dsp_workaround() argument
340 mutex_lock(&phydev->lock); in lan937x_dsp_workaround()
342 rc = phy_read(phydev, LAN87XX_EXT_REG_CTL); in lan937x_dsp_workaround()
356 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, val); in lan937x_dsp_workaround()
360 mutex_unlock(&phydev->lock); in lan937x_dsp_workaround()
365 static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank, in access_ereg() argument
376 rc = phy_write(phydev, offset, val); in access_ereg()
378 rc = phy_read(phydev, offset); in access_ereg()
384 rc = phy_write(phydev, LAN87XX_EXT_REG_WR_DATA, val); in access_ereg()
394 if (phydev->phy_id == PHY_ID_LAN937X) { in access_ereg()
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H A Dnxp-c45-tja11xx-macsec.c290 static int nxp_c45_macsec_write(struct phy_device *phydev, u16 addr, u32 value) in nxp_c45_macsec_write() argument
298 phydev_dbg(phydev, "write addr 0x%x value 0x%x\n", addr, value); in nxp_c45_macsec_write()
301 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, laddr, lvalue); in nxp_c45_macsec_write()
307 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, laddr, lvalue); in nxp_c45_macsec_write()
312 static int nxp_c45_macsec_read(struct phy_device *phydev, u16 addr, u32 *value) in nxp_c45_macsec_read() argument
321 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, laddr); in nxp_c45_macsec_read()
327 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, laddr); in nxp_c45_macsec_read()
334 phydev_dbg(phydev, "read addr 0x%x value 0x%x\n", addr, *value); in nxp_c45_macsec_read()
339 static void nxp_c45_macsec_read32_64(struct phy_device *phydev, u16 addr, in nxp_c45_macsec_read32_64() argument
344 nxp_c45_macsec_read(phydev, addr, &lvalue); in nxp_c45_macsec_read32_64()
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H A Ddp83tg720.c210 static int dp83tg720_update_stats(struct phy_device *phydev) in dp83tg720_update_stats() argument
212 struct dp83tg720_priv *priv = phydev->priv; in dp83tg720_update_stats()
217 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_LINK_QUAL_3); in dp83tg720_update_stats()
235 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_1); in dp83tg720_update_stats()
241 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_2); in dp83tg720_update_stats()
248 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_3); in dp83tg720_update_stats()
254 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_4); in dp83tg720_update_stats()
260 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_5); in dp83tg720_update_stats()
267 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_6); in dp83tg720_update_stats()
276 static int dp83tg720_soft_reset(struct phy_device *phydev) in dp83tg720_soft_reset() argument
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H A Ddp83867.c201 static int dp83867_ack_interrupt(struct phy_device *phydev) in dp83867_ack_interrupt() argument
203 int err = phy_read(phydev, MII_DP83867_ISR); in dp83867_ack_interrupt()
211 static int dp83867_set_wol(struct phy_device *phydev, in dp83867_set_wol() argument
214 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
218 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG); in dp83867_set_wol()
219 val_micr = phy_read(phydev, MII_DP83867_MICR); in dp83867_set_wol()
232 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1, in dp83867_set_wol()
234 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2, in dp83867_set_wol()
236 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3, in dp83867_set_wol()
245 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, in dp83867_set_wol()
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/linux/include/linux/
H A Dphy.h804 void (*phy_link_change)(struct phy_device *phydev, bool up);
822 #define phy_for_each_port(phydev, port) \ argument
823 list_for_each_entry(port, &(phydev)->ports, head)
941 struct phy_device *phydev; member
1142 int (*soft_reset)(struct phy_device *phydev);
1148 int (*config_init)(struct phy_device *phydev);
1154 int (*probe)(struct phy_device *phydev);
1160 int (*get_features)(struct phy_device *phydev);
1167 unsigned int (*inband_caps)(struct phy_device *phydev,
1173 int (*config_inband)(struct phy_device *phydev, unsigned int modes);
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/linux/drivers/net/phy/realtek/
H A Drealtek_main.c348 static int rtl821x_read_page(struct phy_device *phydev) in rtl821x_read_page() argument
350 return __phy_read(phydev, RTL821x_PAGE_SELECT); in rtl821x_read_page()
353 static int rtl821x_write_page(struct phy_device *phydev, int page) in rtl821x_write_page() argument
355 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); in rtl821x_write_page()
358 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page, in rtl821x_read_ext_page() argument
363 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE); in rtl821x_read_ext_page()
365 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page); in rtl821x_read_ext_page()
367 ret = __phy_read(phydev, regnum); in rtl821x_read_ext_page()
370 return phy_restore_page(phydev, oldpage, ret); in rtl821x_read_ext_page()
373 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page, in rtl821x_modify_ext_page() argument
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/linux/drivers/net/phy/qcom/
H A Dat803x.c184 static int at803x_write_page(struct phy_device *phydev, int page) in at803x_write_page() argument
197 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); in at803x_write_page()
200 static int at803x_read_page(struct phy_device *phydev) in at803x_read_page() argument
202 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); in at803x_read_page()
213 static int at803x_enable_rx_delay(struct phy_device *phydev) in at803x_enable_rx_delay() argument
215 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, in at803x_enable_rx_delay()
219 static int at803x_enable_tx_delay(struct phy_device *phydev) in at803x_enable_tx_delay() argument
221 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, in at803x_enable_tx_delay()
225 static int at803x_disable_rx_delay(struct phy_device *phydev) in at803x_disable_rx_delay() argument
227 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTR in at803x_disable_rx_delay()
231 at803x_disable_tx_delay(struct phy_device * phydev) at803x_disable_tx_delay() argument
238 at803x_context_save(struct phy_device * phydev,struct at803x_context * context) at803x_context_save() argument
250 at803x_context_restore(struct phy_device * phydev,const struct at803x_context * context) at803x_context_restore() argument
261 at803x_suspend(struct phy_device * phydev) at803x_suspend() argument
279 at803x_resume(struct phy_device * phydev) at803x_resume() argument
284 at803x_parse_dt(struct phy_device * phydev) at803x_parse_dt() argument
363 at803x_probe(struct phy_device * phydev) at803x_probe() argument
382 at803x_get_features(struct phy_device * phydev) at803x_get_features() argument
412 at803x_smarteee_config(struct phy_device * phydev) at803x_smarteee_config() argument
444 at803x_clk_out_config(struct phy_device * phydev) at803x_clk_out_config() argument
455 at8031_pll_config(struct phy_device * phydev) at8031_pll_config() argument
470 at803x_hibernation_mode_config(struct phy_device * phydev) at803x_hibernation_mode_config() argument
485 at803x_config_init(struct phy_device * phydev) at803x_config_init() argument
531 at803x_link_change_notify(struct phy_device * phydev) at803x_link_change_notify() argument
556 at803x_config_aneg(struct phy_device * phydev) at803x_config_aneg() argument
602 at803x_cable_test_one_pair(struct phy_device * phydev,int pair) at803x_cable_test_one_pair() argument
641 at803x_cable_test_get_status(struct phy_device * phydev,bool * finished,unsigned long pair_mask) at803x_cable_test_get_status() argument
673 at803x_cable_test_autoneg(struct phy_device * phydev) at803x_cable_test_autoneg() argument
683 at803x_cable_test_start(struct phy_device * phydev) at803x_cable_test_start() argument
693 struct phy_device *phydev = rdev_get_drvdata(rdev); at8031_rgmii_reg_set_voltage_sel() local
705 struct phy_device *phydev = rdev_get_drvdata(rdev); at8031_rgmii_reg_get_voltage_sel() local
749 at8031_register_regulators(struct phy_device * phydev) at8031_register_regulators() argument
776 struct phy_device *phydev = port_phydev(port); at803x_configure_mii() local
789 at8031_attach_mii_port(struct phy_device * phydev,struct phy_port * port) at8031_attach_mii_port() argument
811 at8031_parse_dt(struct phy_device * phydev) at8031_parse_dt() argument
834 at8031_probe(struct phy_device * phydev) at8031_probe() argument
878 at8031_config_init(struct phy_device * phydev) at8031_config_init() argument
902 at8031_config_intr(struct phy_device * phydev) at8031_config_intr() argument
926 at8031_read_status(struct phy_device * phydev) at8031_read_status() argument
938 at8031_cable_test_get_status(struct phy_device * phydev,bool * finished) at8031_cable_test_get_status() argument
945 at8031_cable_test_start(struct phy_device * phydev) at8031_cable_test_start() argument
954 at8032_cable_test_get_status(struct phy_device * phydev,bool * finished) at8032_cable_test_get_status() argument
960 at8035_parse_dt(struct phy_device * phydev) at8035_parse_dt() argument
988 at8035_probe(struct phy_device * phydev) at8035_probe() argument
999 ipq5018_cable_test_start(struct phy_device * phydev) ipq5018_cable_test_start() argument
1022 ipq5018_config_init(struct phy_device * phydev) ipq5018_config_init() argument
1064 ipq5018_link_change_notify(struct phy_device * phydev) ipq5018_link_change_notify() argument
1075 ipq5018_probe(struct phy_device * phydev) ipq5018_probe() argument
[all...]
H A Dqca808x.c99 static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) in qca808x_phy_fast_retrain_config() argument
104 ret = genphy_c45_fast_retrain(phydev, true); in qca808x_phy_fast_retrain_config()
108 phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, in qca808x_phy_fast_retrain_config()
110 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, in qca808x_phy_fast_retrain_config()
112 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, in qca808x_phy_fast_retrain_config()
114 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, in qca808x_phy_fast_retrain_config()
116 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, in qca808x_phy_fast_retrain_config()
118 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, in qca808x_phy_fast_retrain_config()
120 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, in qca808x_phy_fast_retrain_config()
122 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, in qca808x_phy_fast_retrain_config()
[all …]
H A Dqcom-phy-lib.c17 int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) in at803x_debug_reg_read() argument
21 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); in at803x_debug_reg_read()
25 return phy_read(phydev, AT803X_DEBUG_DATA); in at803x_debug_reg_read()
29 int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, in at803x_debug_reg_mask() argument
35 ret = at803x_debug_reg_read(phydev, reg); in at803x_debug_reg_mask()
43 return phy_write(phydev, AT803X_DEBUG_DATA, val); in at803x_debug_reg_mask()
47 int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) in at803x_debug_reg_write() argument
51 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); in at803x_debug_reg_write()
55 return phy_write(phydev, AT803X_DEBUG_DATA, data); in at803x_debug_reg_write()
59 int at803x_set_wol(struct phy_device *phydev, in at803x_set_wol() argument
[all …]
/linux/drivers/net/phy/mscc/
H A Dmscc_serdes.c14 static int pll5g_detune(struct phy_device *phydev) in pll5g_detune() argument
19 rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2); in pll5g_detune()
22 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in pll5g_detune()
25 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in pll5g_detune()
29 static int pll5g_tune(struct phy_device *phydev) in pll5g_tune() argument
34 rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2); in pll5g_tune()
36 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in pll5g_tune()
39 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in pll5g_tune()
43 static int vsc85xx_sd6g_pll_cfg_wr(struct phy_device *phydev, in vsc85xx_sd6g_pll_cfg_wr() argument
50 ret = vsc85xx_csr_write(phydev, MACRO_CTRL, in vsc85xx_sd6g_pll_cfg_wr()
[all …]
H A Dmscc_macsec.c22 static u32 vsc8584_macsec_phy_read(struct phy_device *phydev, in vsc8584_macsec_phy_read() argument
29 rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC); in vsc8584_macsec_phy_read()
33 __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_20, in vsc8584_macsec_phy_read()
42 __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_19, in vsc8584_macsec_phy_read()
49 val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19); in vsc8584_macsec_phy_read()
52 val_l = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_17); in vsc8584_macsec_phy_read()
53 val_h = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_18); in vsc8584_macsec_phy_read()
56 phy_restore_page(phydev, rc, rc); in vsc8584_macsec_phy_read()
61 static void vsc8584_macsec_phy_write(struct phy_device *phydev, in vsc8584_macsec_phy_write() argument
67 rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC); in vsc8584_macsec_phy_write()
[all …]
/linux/drivers/net/phy/mediatek/
H A Dmtk-ge-soc.c395 static int cal_cycle(struct phy_device *phydev, int devad, in cal_cycle() argument
401 phy_modify_mmd(phydev, devad, regnum, in cal_cycle()
403 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, in cal_cycle()
406 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, in cal_cycle()
412 phydev_err(phydev, "Calibration cycle timeout\n"); in cal_cycle()
416 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, in cal_cycle()
418 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP); in cal_cycle()
422 phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); in cal_cycle()
427 static int rext_fill_result(struct phy_device *phydev, u16 *buf) in rext_fill_result() argument
429 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, in rext_fill_result()
[all …]

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