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Searched refs:phyclk_mhz (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c127 .phyclk_mhz = 600.0,
136 .phyclk_mhz = 810.0,
145 .phyclk_mhz = 810.0,
154 .phyclk_mhz = 810.0,
163 .phyclk_mhz = 810.0,
371 .phyclk_mhz = 600.0,
380 .phyclk_mhz = 810.0,
389 .phyclk_mhz = 810.0,
398 .phyclk_mhz = 810.0,
407 .phyclk_mhz = 810.0,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c229 .phyclk_mhz = 540.0,
240 .phyclk_mhz = 600.0,
251 .phyclk_mhz = 810.0,
262 .phyclk_mhz = 810.0,
273 .phyclk_mhz = 810.0,
285 .phyclk_mhz = 810.0,
340 .phyclk_mhz = 540.0,
351 .phyclk_mhz = 600.0,
362 .phyclk_mhz = 810.0,
373 .phyclk_mhz = 810.0,
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_socbb.h34 uint32_t phyclk_mhz; member
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c148 .phyclk_mhz = 810.0,
159 .phyclk_mhz = 810.0,
170 .phyclk_mhz = 810.0,
181 .phyclk_mhz = 810.0,
193 .phyclk_mhz = 810.0,
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_translation_helper.c365 p->in_states->state_array[0].phyclk_mhz = 810; in dml2_init_soc_states()
401 p->in_states->state_array[0].phyclk_mhz = 810; in dml2_init_soc_states()
438 p->in_states->state_array[0].phyclk_mhz = 810; in dml2_init_soc_states()
584 if (p->in_states->state_array[i].phyclk_mhz > max_phyclk_mhz) in dml2_init_soc_states()
585 max_phyclk_mhz = (int)p->in_states->state_array[i].phyclk_mhz; in dml2_init_soc_states()
597 p->out_states->state_array[i].phyclk_mhz = max_phyclk_mhz; in dml2_init_soc_states()
600 p->out_states->state_array[i].phyclk_mhz = max_phyclk_mhz; in dml2_init_soc_states()
735 out->state_array[i].phyclk_mhz = dc->dml.soc.clock_limits[i].phyclk_mhz; in dml2_translate_soc_states()
H A Ddml2_wrapper_fpu.c419 …_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].phyclk_mhz * 1000; in dml2_validate_and_build_resource()
477 …_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].phyclk_mhz * 1000; in dml2_validate_and_build_resource()
H A Ddisplay_mode_util.c637 dml_print("DML: state_bbox: phyclk_mhz = %f\n", state->phyclk_mhz); in dml_print_soc_state_bounding_box()
H A Ddisplay_mode_core_structs.h280 dml_float_t phyclk_mhz; member
H A Ddisplay_mode_core.c7182 mode_lib->ms.state.phyclk_mhz, in dml_core_mode_support()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c134 .phyclk_mhz = 810.0,
2650 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn32_patch_dpm_table()
2651 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn32_patch_dpm_table()
2796 if (bw_params->clk_table.entries[i].phyclk_mhz > max_clk_data.phyclk_mhz) in build_synthetic_soc_states()
2797 max_clk_data.phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in build_synthetic_soc_states()
2842 if (max_clk_data.phyclk_mhz == 0) in build_synthetic_soc_states()
2843 max_clk_data.phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; in build_synthetic_soc_states()
2850 entry.phyclk_mhz = max_clk_data.phyclk_mhz; in build_synthetic_soc_states()
3139 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn32_update_bw_bounding_box_fpu()
3140 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn32_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h167 double phyclk_mhz; member
H A Ddisplay_mode_vba.c398 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; in fetch_socbb_params()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c2168 if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz) in dcn30_update_bw_bounding_box()
2169 dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn30_update_bw_bounding_box()