Searched refs:phy_ref_clk (Results 1 – 3 of 3) sorted by relevance
127 struct clk *phy_ref_clk; member191 unsigned long ref_clk = clk_get_rate(priv->phy_ref_clk); in mixel_dphy_config_from_opts()436 clk_set_rate(priv->phy_ref_clk, lvds_opts->differential_clk_rate); in mixel_dphy_configure_lvds_phy()570 ret = clk_prepare_enable(priv->phy_ref_clk); in mixel_dphy_power_on()590 clk_disable_unprepare(priv->phy_ref_clk); in mixel_dphy_power_on()604 clk_disable_unprepare(priv->phy_ref_clk); in mixel_dphy_power_off()692 priv->phy_ref_clk = devm_clk_get(&pdev->dev, "phy_ref"); in mixel_dphy_probe()693 if (IS_ERR(priv->phy_ref_clk)) { in mixel_dphy_probe()695 return PTR_ERR(priv->phy_ref_clk); in mixel_dphy_probe()698 clk_get_rate(priv->phy_ref_clk)); in mixel_dphy_probe()
131 struct clk *phy_ref_clk; member153 phy->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref"); in hi3660_pcie_phy_get_clk()154 if (IS_ERR(phy->phy_ref_clk)) in hi3660_pcie_phy_get_clk()155 return PTR_ERR(phy->phy_ref_clk); in hi3660_pcie_phy_get_clk()243 ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ); in hi3660_pcie_phy_clk_ctrl()247 ret = clk_prepare_enable(phy->phy_ref_clk); in hi3660_pcie_phy_clk_ctrl()278 clk_disable_unprepare(phy->phy_ref_clk); in hi3660_pcie_phy_clk_ctrl()
52 - "phy_ref_clk"84 - "phy_ref_clk"139 clock-names = "phy_ref_clk", "apb_pclk";