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Searched refs:phy_inst (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddccg.h267 int phy_inst,
273 int phy_inst,
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gc_9_4_3.c228 unsigned int phy_inst = GET_INST(GC, xcc_inst); in kgd_gfx_v9_4_3_set_pasid_vmid_mapping() local
230 unsigned int aid = phy_inst / 2; in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
267 aid * 4 + (phy_inst % 2) + 1); in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_crc.c349 uint8_t phy_inst; in amdgpu_dm_crtc_notify_ta_to_read() local
377 if (!get_phy_id(dm, aconnector, &phy_inst)) { in amdgpu_dm_crtc_notify_ta_to_read()
397 securedisplay_cmd->securedisplay_in_message.send_roi_crc_v2.phy_id = phy_inst; in amdgpu_dm_crtc_notify_ta_to_read()
410 securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = phy_inst; in amdgpu_dm_crtc_notify_ta_to_read()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
H A Ddcn35_dccg.c1543 int phy_inst, in dccg35_set_physymclk_root_clock_gating() argument
1551 switch (phy_inst) { in dccg35_set_physymclk_root_clock_gating()
1576 …DC_LOG_DEBUG("%s: dpp_inst(%d) PHYESYMCLK_ROOT_GATE_DISABLE: %d\n", __func__, phy_inst, enable ? 0… in dccg35_set_physymclk_root_clock_gating()
1582 int phy_inst, in dccg35_set_physymclk() argument
1589 switch (phy_inst) { in dccg35_set_physymclk()
1650 __func__, phy_inst, force_enable ? 1 : 0, clk_src); in dccg35_set_physymclk()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
H A Ddcn401_dccg.c270 int phy_inst, in dccg401_set_physymclk() argument
277 switch (phy_inst) { in dccg401_set_physymclk()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
H A Ddcn31_dccg.c445 int phy_inst, in dccg31_set_physymclk() argument
452 switch (phy_inst) { in dccg31_set_physymclk()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c503 void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_inst, bool clock_on) in dcn35_physymclk_root_clock_control() argument
510 hws->ctx->dc->res_pool->dccg, phy_inst, clock_on); in dcn35_physymclk_root_clock_control()
/linux/drivers/gpu/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h6257 uint8_t phy_inst; /**< phy inst for cable id data */ member