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Searched refs:phy_clear_bits (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/net/phy/
H A Dnxp-tja11xx.c143 return phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL); in tja11xx_disable_link_control()
162 ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST); in tja11xx_wakeup()
351 ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM); in tja11xx_config_init()
735 ret = phy_clear_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); in tja11xx_cable_test_start()
H A Dbroadcom.c191 rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); in bcm54616s_config_init()
202 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); in bcm54616s_config_init()
H A Dsmsc.c97 return phy_clear_bits(phydev, MII_LAN83C185_CTRL_STATUS, in smsc_phy_config_edpd()
H A Dmarvell.c1098 err = phy_clear_bits(phydev, MII_M1111_PHY_EXT_CR, in m88e1111_set_downshift()
1162 err = phy_clear_bits(phydev, MII_M1011_PHY_SCR, in m88e1011_set_downshift()
1556 return phy_clear_bits(phydev, MII_88E1540_COPPER_CTRL3, in m88e1540_set_fld()
2379 ret = phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE); in marvell_cable_test_start_common()
H A Ddp83869.c457 return phy_clear_bits(phydev, DP83869_CFG2, in dp83869_set_downshift()
H A Dmicrel.c835 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST); in ksz8081_config_init()
2073 ret = phy_clear_bits(phydev, MII_KSZPHY_CTRL, in ksz886x_config_aneg()
2849 return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100); in ksz886x_cable_test_start()
H A Dphy_device.c2823 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); in genphy_resume()
/linux/drivers/net/phy/mediatek/
H A Dmtk-ge-soc.c1479 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); in an7583_phy_config_init()
/linux/include/linux/
H A Dphy.h1914 static inline int phy_clear_bits(struct phy_device *phydev, u32 regnum, u16 val) in phy_clear_bits() function