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Searched refs:phase (Results 1 – 25 of 251) sorted by relevance

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/linux/drivers/clk/hisilicon/
H A Dclk-hisi-phase.c30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
50 return hisi_phase_regval_to_degrees(phase, regval); in hisi_clk_get_phase()
53 static int hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase, in hisi_phase_degrees_to_regval() argument
58 for (i = 0; i < phase->phase_num; i++) in hisi_phase_degrees_to_regval()
[all …]
/linux/drivers/clk/sunxi-ng/
H A Dccu_phase.c15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
58 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
110 spin_lock_irqsave(phase->common.lock, flags); in ccu_phase_set_phase()
111 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
112 reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift); in ccu_phase_set_phase()
113 writel(reg | (delay << phase->shift), in ccu_phase_set_phase()
114 phase->common.base + phase->common.reg); in ccu_phase_set_phase()
[all …]
/linux/drivers/clk/sunxi/
H A Dclk-mod0.c173 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_get_phase() local
179 value = readl(phase->reg); in mmc_get_phase()
180 delay = (value >> phase->offset) & 0x3; in mmc_get_phase()
215 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_set_phase() local
266 spin_lock_irqsave(phase->lock, flags); in mmc_set_phase()
267 value = readl(phase->reg); in mmc_set_phase()
268 value &= ~GENMASK(phase->offset + 3, phase->offset); in mmc_set_phase()
269 value |= delay << phase->offset; in mmc_set_phase()
270 writel(value, phase->reg); in mmc_set_phase()
271 spin_unlock_irqrestore(phase->lock, flags); in mmc_set_phase()
[all …]
/linux/drivers/char/
H A Dppdev.c404 pp->saved_state.phase = info->phase; in pp_do_ioctl()
406 info->phase = pp->state.phase; in pp_do_ioctl()
435 pp->state.phase = init_phase(mode); in pp_do_ioctl()
439 pp->pdev->port->ieee1284.phase = pp->state.phase; in pp_do_ioctl()
459 int phase; in pp_do_ioctl() local
461 if (copy_from_user(&phase, argp, sizeof(phase))) in pp_do_ioctl()
465 pp->state.phase = phase; in pp_do_ioctl()
468 pp->pdev->port->ieee1284.phase = phase; in pp_do_ioctl()
474 int phase; in pp_do_ioctl() local
477 phase = pp->pdev->port->ieee1284.phase; in pp_do_ioctl()
[all …]
/linux/drivers/gpu/drm/imx/dcss/
H A Ddcss-scaler.c179 int phase; in dcss_scaler_gaussian_filter() local
184 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
185 coef[phase][0] = 0; in dcss_scaler_gaussian_filter()
186 coef[phase][PSC_NUM_TAPS - 1] = 0; in dcss_scaler_gaussian_filter()
233 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
238 sum += coef[phase][i]; in dcss_scaler_gaussian_filter()
240 ll_temp = coef[phase][i]; in dcss_scaler_gaussian_filter()
244 coef[phase][i] = (int)ll_temp; in dcss_scaler_gaussian_filter()
577 int i, phase; in dcss_scaler_program_5_coef_set() local
593 for (phase = (PSC_NUM_PHASES >> 1) - 1; in dcss_scaler_program_5_coef_set()
[all …]
/linux/drivers/hwmon/pmbus/
H A Dmp2975.c142 mp2975_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg, in mp2975_read_word_helper() argument
145 int ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_word_helper()
204 int page, int phase, u8 reg) in mp2975_read_phase() argument
208 ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_phase()
212 if (!((phase + 1) % MP2975_PAGE_NUM)) in mp2975_read_phase()
235 ret = pmbus_read_word_data(client, page, phase, PMBUS_READ_IOUT); in mp2975_read_phase()
245 int page, int phase) in mp2975_read_phases() argument
250 switch (phase) { in mp2975_read_phases()
252 ret = mp2975_read_phase(client, data, page, phase, in mp2975_read_phases()
256 ret = mp2975_read_phase(client, data, page, phase, in mp2975_read_phases()
[all …]
H A Dlt3074.c25 int phase, int reg) in lt3074_read_word_data() argument
29 return pmbus_read_word_data(client, page, phase, in lt3074_read_word_data()
32 return pmbus_read_word_data(client, page, phase, in lt3074_read_word_data()
35 return pmbus_read_word_data(client, page, phase, in lt3074_read_word_data()
/linux/lib/zstd/compress/
H A Dzstd_cwksp.h168 ZSTD_cwksp_alloc_phase_e phase; member
303 ZSTD_cwksp_internal_advance_phase(ZSTD_cwksp* ws, ZSTD_cwksp_alloc_phase_e phase) in ZSTD_cwksp_internal_advance_phase() argument
305 assert(phase >= ws->phase); in ZSTD_cwksp_internal_advance_phase()
306 if (phase > ws->phase) { in ZSTD_cwksp_internal_advance_phase()
308 if (ws->phase < ZSTD_cwksp_alloc_aligned_init_once && in ZSTD_cwksp_internal_advance_phase()
309 phase >= ZSTD_cwksp_alloc_aligned_init_once) { in ZSTD_cwksp_internal_advance_phase()
327 ws->phase = phase; in ZSTD_cwksp_internal_advance_phase()
345 ZSTD_cwksp_reserve_internal(ZSTD_cwksp* ws, size_t bytes, ZSTD_cwksp_alloc_phase_e phase) in ZSTD_cwksp_reserve_internal() argument
348 if (ZSTD_isError(ZSTD_cwksp_internal_advance_phase(ws, phase)) || bytes == 0) { in ZSTD_cwksp_reserve_internal()
413 const ZSTD_cwksp_alloc_phase_e phase = ZSTD_cwksp_alloc_aligned_init_once; in ZSTD_cwksp_reserve_table() local
[all …]
/linux/drivers/parport/
H A Dieee1284_ops.c52 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; in parport_ieee1284_write_compat()
138 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_ieee1284_write_compat()
171 port->ieee1284.phase = IEEE1284_PH_REV_DATA; in parport_ieee1284_read_nibble()
221 port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE; in parport_ieee1284_read_nibble()
224 port->physport->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL; in parport_ieee1284_read_nibble()
259 port->physport->ieee1284.phase = IEEE1284_PH_REV_DATA; in parport_ieee1284_read_byte()
306 port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE; in parport_ieee1284_read_byte()
309 port->physport->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL; in parport_ieee1284_read_byte()
345 port->ieee1284.phase = IEEE1284_PH_REV_IDLE; in ecp_forward_to_reverse()
348 port->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN; in ecp_forward_to_reverse()
[all …]
H A Dieee1284.c242 if (port->ieee1284.phase != IEEE1284_PH_FWD_IDLE) { in parport_ieee1284_terminate()
260 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_ieee1284_terminate()
296 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_ieee1284_terminate()
364 port->ieee1284.phase = IEEE1284_PH_NEGOTIATION; in parport_negotiate()
401 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_negotiate()
498 port->ieee1284.phase = IEEE1284_PH_ECP_SETUP; in parport_negotiate()
513 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_negotiate()
518 port->ieee1284.phase = IEEE1284_PH_REV_IDLE; in parport_negotiate()
521 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_negotiate()
544 port->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL; in parport_ieee1284_ack_data_avail()
[all …]
/linux/drivers/net/wwan/iosm/
H A Diosm_ipc_imem_ops.c19 ipc_imem_phase_get_string(ipc_imem->phase), if_id); in ipc_imem_sys_wwan_open()
24 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_open()
66 if (ipc_imem->phase != IPC_P_RUN) { in ipc_imem_sys_wwan_transmit()
68 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_transmit()
146 enum ipc_phase phase; in ipc_imem_is_channel_active() local
149 phase = ipc_imem->phase; in ipc_imem_is_channel_active()
152 switch (phase) { in ipc_imem_is_channel_active()
174 channel->channel_id, phase); in ipc_imem_is_channel_active()
203 curr_phase = ipc_imem->phase; in ipc_imem_sys_port_close()
294 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_port_open()
[all …]
H A Diosm_ipc_imem.c291 ipc_imem_phase_get_string(ipc_imem->phase), in ipc_imem_ipc_init_check()
540 return (ipc_imem->phase == IPC_P_RUN && in ipc_imem_get_exec_stage_buffered()
572 if (ipc_imem->phase != IPC_P_RUN) { in ipc_imem_run_state_worker()
645 enum ipc_phase old_phase, phase; in ipc_imem_handle_irq() local
654 old_phase = ipc_imem->phase; in ipc_imem_handle_irq()
664 phase = ipc_imem_phase_update(ipc_imem); in ipc_imem_handle_irq()
666 switch (phase) { in ipc_imem_handle_irq()
704 ipc_imem_phase_get_string(phase)); in ipc_imem_handle_irq()
772 if ((phase == IPC_P_PSI || phase == IPC_P_EBL) && in ipc_imem_handle_irq()
814 if (ipc_imem->phase != IPC_P_ROM) { in ipc_imem_phase_update_check()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/
H A Ddcn21_dccg.c53 int phase; in dccg21_update_dpp_dto() local
67 phase = (req_dppclk + 9999) / 10000; in dccg21_update_dpp_dto()
69 if (phase > modulo) { in dccg21_update_dpp_dto()
74 phase = modulo; in dccg21_update_dpp_dto()
85 phase = 10; in dccg21_update_dpp_dto()
89 DPPCLK0_DTO_PHASE, phase, in dccg21_update_dpp_dto()
/linux/fs/
H A Dfsopen.c147 fc->phase = FS_CONTEXT_CREATE_PARAMS; in SYSCALL_DEFINE2()
200 fc->phase = FS_CONTEXT_RECONF_PARAMS; in SYSCALL_DEFINE3()
222 if (fc->phase != FS_CONTEXT_CREATE_PARAMS) in vfs_cmd_create()
228 fc->phase = FS_CONTEXT_CREATING; in vfs_cmd_create()
233 fc->phase = FS_CONTEXT_FAILED; in vfs_cmd_create()
241 fc->phase = FS_CONTEXT_FAILED; in vfs_cmd_create()
247 fc->phase = FS_CONTEXT_AWAITING_MOUNT; in vfs_cmd_create()
256 if (fc->phase != FS_CONTEXT_RECONF_PARAMS) in vfs_cmd_reconfigure()
259 fc->phase = FS_CONTEXT_RECONFIGURING; in vfs_cmd_reconfigure()
263 fc->phase = FS_CONTEXT_FAILED; in vfs_cmd_reconfigure()
[all …]
/linux/drivers/char/ipmi/
H A Dkcs_bmc_cdev_ipmi.c76 enum kcs_ipmi_phases phase; member
133 priv->phase = KCS_PHASE_ERROR; in kcs_bmc_ipmi_force_abort()
145 switch (priv->phase) { in kcs_bmc_ipmi_handle_data()
147 priv->phase = KCS_PHASE_WRITE_DATA; in kcs_bmc_ipmi_handle_data()
165 priv->phase = KCS_PHASE_WRITE_DONE; in kcs_bmc_ipmi_handle_data()
187 priv->phase = KCS_PHASE_IDLE; in kcs_bmc_ipmi_handle_data()
198 priv->phase = KCS_PHASE_ABORT_ERROR2; in kcs_bmc_ipmi_handle_data()
205 priv->phase = KCS_PHASE_IDLE; in kcs_bmc_ipmi_handle_data()
224 priv->phase = KCS_PHASE_WRITE_START; in kcs_bmc_ipmi_handle_cmd()
231 if (priv->phase != KCS_PHASE_WRITE_DATA) { in kcs_bmc_ipmi_handle_cmd()
[all …]
/linux/include/trace/events/
H A Dclk.h200 TP_PROTO(struct clk_core *core, int phase),
202 TP_ARGS(core, phase),
206 __field( int, phase )
211 __entry->phase = phase;
214 TP_printk("%s %d", __get_str(name), (int)__entry->phase)
219 TP_PROTO(struct clk_core *core, int phase),
221 TP_ARGS(core, phase)
226 TP_PROTO(struct clk_core *core, int phase),
228 TP_ARGS(core, phase)
[all...]
/linux/drivers/scsi/pcmcia/
H A Dnsp_cs.c231 scsi_pointer->phase = PH_UNDETERMINED; in nsp_queuecommand_lck()
371 unsigned char phase, arbit; in nsphw_start_selection() local
375 phase = nsp_index_read(base, SCSIBUSMON); in nsphw_start_selection()
376 if(phase != BUSMON_BUS_FREE) { in nsphw_start_selection()
383 scsi_pointer->phase = PH_ARBSTART; in nsphw_start_selection()
403 scsi_pointer->phase = PH_SELSTART; in nsphw_start_selection()
548 unsigned char phase, i_src; in nsp_expect_signal() local
554 phase = nsp_index_read(base, SCSIBUSMON); in nsp_expect_signal()
555 if (phase == 0xff) { in nsp_expect_signal()
564 if ((phase & mask) != 0 && (phase & BUSMON_PHASE_MASK) == current_phase) { in nsp_expect_signal()
[all …]
/linux/drivers/leds/trigger/
H A Dledtrig-heartbeat.c27 unsigned int phase; member
52 switch (heartbeat_data->phase) { in led_heartbeat_function()
65 heartbeat_data->phase++; in led_heartbeat_function()
71 heartbeat_data->phase++; in led_heartbeat_function()
77 heartbeat_data->phase++; in led_heartbeat_function()
84 heartbeat_data->phase = 0; in led_heartbeat_function()
140 heartbeat_data->phase = 0; in heartbeat_trig_activate()
/linux/drivers/staging/iio/Documentation/
H A Dsysfs-bus-iio-dds36 Stores phase into Y.
40 control the desired phase Y which is added to the phase
48 the desired value in rad. If shared across all phase registers
56 Specifies the active phase Y which is added to the phase
68 phase is controlled by the respective phase and frequency
/linux/tools/power/pm-graph/
H A Dsleepgraph.py1466 # contents: times for phase start/end, order/color data for html
1468 # device callback or action list for this phase
1548 for phase in sorted(self.dmesg.keys()):
1549 if '*' in phase:
1550 p = phase.split('*')
1552 self.dmesg[pnew] = self.dmesg.pop(phase)
1554 for phase in self.sortedPhases():
1555 self.devicegroups.append([phase])
1556 def nextPhase(self, phase, offset): argument
1557 order = self.dmesg[phase]['orde
1884 setPhase(self, phase, ktime, isbegin, order=-1) global() argument
1913 sortedDevices(self, phase) global() argument
1916 fixupInitcalls(self, phase) global() argument
1998 newAction(self, phase, name, pid, parent, start, end, drv, htmlclass='', color='') global() argument
2019 findDevice(self, phase, name) global() argument
2028 deviceChildren(self, devname, phase) global() argument
2035 maxDeviceNameSize(self, phase) global() argument
2748 __init__(self, test, phase, dev) global() argument
2917 phaseRowHeight(self, test, phase, row) global() argument
2919 phaseRowTop(self, test, phase, row) global() argument
[all...]
H A Dbootgraph.py237 def newAction(self, phase, name, pid, start, end, ret, ulen): argument
241 list = self.dmesg[phase]['list']
281 for phase in self.phases:
282 dc = len(self.dmesg[phase]['list'])
283 sysvals.vprint('%9s mode: %.3f - %.3f (%d initcalls)' % (phase,
284 self.dmesg[phase]['start']*1000,
285 self.dmesg[phase]['end']*1000, dc))
295 phase = 'kernel'
359 data.newAction(phase, f, pid, start, ktime, int(r), int(t))
366 phase = 'user'
[all …]
/linux/drivers/mmc/host/
H A Ddw_mmc-rockchip.c182 struct mmc_clk_phase phase = host->phase_map.phase[ios->timing]; in dw_mci_rk3288_set_ios() local
220 sample_phase = phase.valid ? phase.in_deg : priv->default_sample_phase; in dw_mci_rk3288_set_ios()
222 } else if (phase.valid) { in dw_mci_rk3288_set_ios()
223 rockchip_mmc_set_phase(host, true, phase.in_deg); in dw_mci_rk3288_set_ios()
287 if (phase.valid) in dw_mci_rk3288_set_ios()
288 drv_phase = phase.out_deg; in dw_mci_rk3288_set_ios()
312 int phase; in dw_mci_rk3288_execute_tuning() local
412 phase = TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases); in dw_mci_rk3288_execute_tuning()
413 dev_info(host->dev, "Successfully tuned phase to %d\n", phase); in dw_mci_rk3288_execute_tuning()
415 rockchip_mmc_set_phase(host, true, phase); in dw_mci_rk3288_execute_tuning()
H A Dmmci_stm32_sdmmc.c71 int phase, bool sampler __maybe_unused);
488 int unit, int phase, bool sampler) in sdmmc_dlyb_mp15_set_cfg() argument
495 FIELD_PREP(DLYB_CFGR_SEL_MASK, phase); in sdmmc_dlyb_mp15_set_cfg()
552 int unit __maybe_unused, int phase, in sdmmc_dlyb_mp25_set_cfg() argument
559 cr |= FIELD_PREP(DLYBSD_CR_RXTAPSEL_MASK, phase); in sdmmc_dlyb_mp25_set_cfg()
581 int phase, ret; in sdmmc_dlyb_phase_tuning() local
583 for (phase = 0; phase <= dlyb->max; phase++) { in sdmmc_dlyb_phase_tuning()
584 ret = dlyb->ops->set_cfg(dlyb, dlyb->unit, phase, false); in sdmmc_dlyb_phase_tuning()
596 end_of_len = phase; in sdmmc_dlyb_phase_tuning()
609 phase = end_of_len - max_len / 2; in sdmmc_dlyb_phase_tuning()
[all …]
/linux/drivers/scsi/
H A Dmac53c94.c54 enum fsc_phase phase; /* what we're currently trying to do */ member
95 if (state->phase == idle) in mac53c94_queue_lck()
150 if (state->phase != idle || state->current_req != NULL) in mac53c94_start()
175 state->phase = selecting; in mac53c94_start()
211 intr, stat, seq, state->phase); in mac53c94_interrupt()
224 intr, stat, seq, state->phase); in mac53c94_interrupt()
232 intr, stat, seq, state->phase); in mac53c94_interrupt()
246 switch (state->phase) { in mac53c94_interrupt()
277 state->phase = dataing; in mac53c94_interrupt()
282 state->phase = completing; in mac53c94_interrupt()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c53 int modulo, phase; in dccg2_update_dpp_dto() local
57 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg2_update_dpp_dto()
59 if (phase > 0xff) { in dccg2_update_dpp_dto()
61 phase = 0xff; in dccg2_update_dpp_dto()
65 DPPCLK0_DTO_PHASE, phase, in dccg2_update_dpp_dto()

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