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Searched refs:peri_cg_regs (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt6735-pericfg.c23 static struct mtk_gate_regs peri_cg_regs = { variable
30 GATE_MTK(CLK_PERI_DISP_PWM, "disp_pwm", "disppwm_sel", &peri_cg_regs, 0, &mtk_clk_gate_ops_setclr),
31 GATE_MTK(CLK_PERI_THERM, "therm", "axi_sel", &peri_cg_regs, 1, &mtk_clk_gate_ops_setclr),
32 GATE_MTK(CLK_PERI_PWM1, "pwm1", "axi_sel", &peri_cg_regs, 2, &mtk_clk_gate_ops_setclr),
33 GATE_MTK(CLK_PERI_PWM2, "pwm2", "axi_sel", &peri_cg_regs, 3, &mtk_clk_gate_ops_setclr),
34 GATE_MTK(CLK_PERI_PWM3, "pwm3", "axi_sel", &peri_cg_regs, 4, &mtk_clk_gate_ops_setclr),
35 GATE_MTK(CLK_PERI_PWM4, "pwm4", "axi_sel", &peri_cg_regs, 5, &mtk_clk_gate_ops_setclr),
36 GATE_MTK(CLK_PERI_PWM5, "pwm5", "axi_sel", &peri_cg_regs, 6, &mtk_clk_gate_ops_setclr),
37 GATE_MTK(CLK_PERI_PWM6, "pwm6", "axi_sel", &peri_cg_regs, 7, &mtk_clk_gate_ops_setclr),
38 GATE_MTK(CLK_PERI_PWM7, "pwm7", "axi_sel", &peri_cg_regs, 8, &mtk_clk_gate_ops_setclr),
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H A Dclk-mt6795-pericfg.c16 GATE_MTK(_id, _name, _parent, &peri_cg_regs, \
21 static const struct mtk_gate_regs peri_cg_regs = { variable
H A Dclk-mt8183.c809 static const struct mtk_gate_regs peri_cg_regs = { variable
816 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \
H A Dclk-mt8365.c754 static const struct mtk_gate_regs peri_cg_regs = { variable
761 GATE_MTK(CLK_PERIAXI, "periaxi", "axi_sel", &peri_cg_regs, 31,
H A Dclk-mt8192.c915 static const struct mtk_gate_regs peri_cg_regs = { variable
922 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)