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Searched refs:pcw_chg_addr (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-pll.c117 chg = readl(pll->pcw_chg_addr) | in mtk_pll_set_rate_regs()
119 writel(chg, pll->pcw_chg_addr); in mtk_pll_set_rate_regs()
300 pll->pcw_chg_addr = base + data->pcw_chg_reg; in mtk_clk_register_pll_ops()
302 pll->pcw_chg_addr = pll->base_addr + REG_CON1; in mtk_clk_register_pll_ops()
H A Dclk-pll.h69 void __iomem *pcw_chg_addr; member