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Searched refs:pcw (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-pll.c41 u32 pcw, int postdiv) in __mtk_pll_recalc_rate() argument
54 vco = (u64)fin * pcw; in __mtk_pll_recalc_rate()
93 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, in mtk_pll_set_rate_regs() argument
115 val |= pcw << pll->data->pcw_shift; in mtk_pll_set_rate_regs()
138 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, in mtk_pll_calc_values() argument
172 *pcw = (u32)_pcw; in mtk_pll_calc_values()
179 u32 pcw = 0; in mtk_pll_set_rate() local
182 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); in mtk_pll_set_rate()
183 mtk_pll_set_rate_regs(pll, pcw, postdiv); in mtk_pll_set_rate()
192 u32 pcw; in mtk_pll_recalc_rate() local
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H A Dclk-pllfh.c32 u32 pcw = 0; in mtk_fhctl_set_rate() local
35 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); in mtk_fhctl_set_rate()
37 return fh->ops->hopping(fh, pcw, postdiv); in mtk_fhctl_set_rate()
H A Dclk-pll.h95 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
/linux/drivers/phy/mediatek/
H A Dphy-mtk-mipi-dsi-mt8183.c52 u64 pcw; in mtk_mipi_tx_pll_enable() local
81 pcw = div_u64(((u64)mipi_tx->data_rate * txdiv) << 24, 26000000); in mtk_mipi_tx_pll_enable()
82 writel(pcw, base + MIPITX_PLL_CON0); in mtk_mipi_tx_pll_enable()
H A Dphy-mtk-hdmi-mt8195.c215 u64 tmds_clk, pixel_clk, da_hdmitx21_ref_ck, ns_hdmipll_ck, pcw; in mtk_hdmi_pll_calc()
271 * formula: pcw=(frequency_out*2^pcw_bit) / frequency_in / FBKDIV_HS3; in mtk_hdmi_pll_calc()
275 pcw = div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH, in mtk_hdmi_pll_calc()
278 if (pcw > GENMASK_ULL(32, 0)) in mtk_hdmi_pll_calc()
281 fbkdiv_high = FIELD_GET(GENMASK_ULL(63, 32), pcw); in mtk_hdmi_pll_calc()
282 fbkdiv_low = FIELD_GET(GENMASK(31, 0), pcw); in mtk_hdmi_pll_calc()
213 u64 tmds_clk, pixel_clk, da_hdmitx21_ref_ck, ns_hdmipll_ck, pcw; mtk_hdmi_pll_calc() local
H A Dphy-mtk-mipi-dsi-mt8173.c127 u64 pcw; in mtk_mipi_tx_pll_prepare() local
196 pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24, 26000000); in mtk_mipi_tx_pll_prepare()
197 writel(pcw, base + MIPITX_DSI_PLL_CON2); in mtk_mipi_tx_pll_prepare()
/linux/drivers/ptp/
H A Dptp_fc3.c458 s64 pcw; in _idtfc3_adjphase() local
472 pcw = div_s64((s64)delta * idtfc3->tdc_apll_freq * 124, NSEC_PER_SEC); in _idtfc3_adjphase()
474 put_unaligned_le64(pcw, buf); in _idtfc3_adjphase()