Searched refs:parent_idx (Results 1 – 9 of 9) sorted by relevance
1031 u16 parent_idx; member1063 table->parent_idx = PVR_IDX_INVALID; in pvr_page_table_l1_init()1207 u16 parent_idx; member1239 table->parent_idx = PVR_IDX_INVALID; in pvr_page_table_l0_init()1486 child_table->parent_idx = op_ctx->curr_page.l2_idx; in pvr_page_table_l2_insert()1507 op_ctx->curr_page.l1_table->parent_idx); in pvr_page_table_l2_remove()1513 l2_table->entries[op_ctx->curr_page.l1_table->parent_idx] = NULL; in pvr_page_table_l2_remove()1514 op_ctx->curr_page.l1_table->parent_idx = PVR_IDX_INVALID; in pvr_page_table_l2_remove()1547 child_table->parent_idx = op_ctx->curr_page.l1_idx; in pvr_page_table_l1_insert()1569 op_ctx->curr_page.l0_table->parent_idx); in pvr_page_table_l1_remove()[all …]
83 u32 parent_idx = (readl(base + CPG_CKSCR) >> 28) & 3; in sh73a0_cpg_register_clock() local85 parent_name = of_clk_get_parent_name(np, parent_idx >> 1); in sh73a0_cpg_register_clock()86 div = (parent_idx & 1) + 1; in sh73a0_cpg_register_clock()
28 u8 parent_idx[ICE_DPLL_RCLK_NUM_MAX]; member
1814 parent = pf->dplls.inputs[rclk->parent_idx[i]].pin; in ice_dpll_deinit_rclk_pin()1856 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[i]].pin; in ice_dpll_init_rclk_pins()1872 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[--i]].pin; in ice_dpll_init_rclk_pins()2350 pf->dplls.rclk.parent_idx[i] = d->base_rclk_idx + i; in ice_dpll_init_info()
199 collection->parent_idx = (collection->level == 0) ? -1 : in open_collection()1123 while (collection->parent_idx != -1 && in hid_apply_multiplier_to_field()1125 collection = &hid->collection[collection->parent_idx]; in hid_apply_multiplier_to_field()1127 if (collection->parent_idx != -1 || in hid_apply_multiplier_to_field()1163 while (multiplier_collection->parent_idx != -1 && in hid_apply_multiplier()1165 multiplier_collection = &hid->collection[multiplier_collection->parent_idx]; in hid_apply_multiplier()1311 device->collection[i].parent_idx = -1; in hid_open_report()
1140 int parent_idx, in bcm2835_clock_choose_div_and_prate() argument1153 parent = clk_hw_get_parent_by_index(hw, parent_idx); in bcm2835_clock_choose_div_and_prate()1155 if (!(BIT(parent_idx) & data->set_rate_parent)) { in bcm2835_clock_choose_div_and_prate()
891 dpll_pin_on_pin_state_set(struct dpll_pin *pin, u32 parent_idx, in dpll_pin_on_pin_state_set() argument908 parent = xa_load(&dpll_pin_xa, parent_idx); in dpll_pin_on_pin_state_set()
1262 uint8_t parent_idx; member
463 int parent_idx; /* device->collection */ member