Searched refs:parent1 (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/clk/davinci/ |
| H A D | da8xx-cfgchip.c | 198 const char *parent1; member
242 const char * const parent_names[] = { info->parent0, info->parent1 }; in da8xx_cfgchip_mux_clk_register()
272 .parent1 = "div4.5",
294 .parent1 = "pll1_sysclk2",
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| /linux/drivers/clk/ |
| H A D | clk_test.c | 557 struct clk *parent1, *parent2; in clk_test_multiple_parents_mux_set_range_set_parent_get_rate() local
563 parent1 = clk_hw_get_clk_kunit(test, &ctx->parents_ctx[0].hw, NULL); in clk_test_multiple_parents_mux_set_range_set_parent_get_rate()
564 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent1); in clk_test_multiple_parents_mux_set_range_set_parent_get_rate()
565 KUNIT_ASSERT_TRUE(test, clk_is_match(clk_get_parent(clk), parent1)); in clk_test_multiple_parents_mux_set_range_set_parent_get_rate()
570 ret = clk_set_rate(parent1, DUMMY_CLOCK_RATE_1); in clk_test_multiple_parents_mux_set_range_set_parent_get_rate()
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