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Searched refs:par (Results 1 – 25 of 282) sorted by relevance

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/linux/drivers/video/fbdev/nvidia/
H A Dnv_setup.c60 void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value) in NVWriteCrtc() argument
62 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); in NVWriteCrtc()
63 VGA_WR08(par->PCIO, par->IOBase + 0x05, value); in NVWriteCrtc()
65 u8 NVReadCrtc(struct nvidia_par *par, u8 index) in NVReadCrtc() argument
67 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); in NVReadCrtc()
68 return (VGA_RD08(par->PCIO, par->IOBase + 0x05)); in NVReadCrtc()
70 void NVWriteGr(struct nvidia_par *par, u8 index, u8 value) in NVWriteGr() argument
72 VGA_WR08(par->PVIO, VGA_GFX_I, index); in NVWriteGr()
73 VGA_WR08(par->PVIO, VGA_GFX_D, value); in NVWriteGr()
75 u8 NVReadGr(struct nvidia_par *par, u8 index) in NVReadGr() argument
[all …]
H A Dnv_hw.c57 void NVLockUnlock(struct nvidia_par *par, int Lock) in NVLockUnlock() argument
61 VGA_WR08(par->PCIO, 0x3D4, 0x1F); in NVLockUnlock()
62 VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57); in NVLockUnlock()
64 VGA_WR08(par->PCIO, 0x3D4, 0x11); in NVLockUnlock()
65 cr11 = VGA_RD08(par->PCIO, 0x3D5); in NVLockUnlock()
70 VGA_WR08(par->PCIO, 0x3D5, cr11); in NVLockUnlock()
73 int NVShowHideCursor(struct nvidia_par *par, int ShowHide) in NVShowHideCursor() argument
75 int cur = par->CurrentState->cursor1; in NVShowHideCursor()
77 par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) | in NVShowHideCursor()
79 VGA_WR08(par->PCIO, 0x3D4, 0x31); in NVShowHideCursor()
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H A Dnv_accel.c76 struct nvidia_par *par = info->par; in nvidiafb_safe_mode() local
80 par->lockup = 1; in nvidiafb_safe_mode()
85 struct nvidia_par *par = info->par; in NVFlush() local
88 while (--count && READ_GET(par) != par->dmaPut) ; in NVFlush()
98 struct nvidia_par *par = info->par; in NVSync() local
101 while (--count && NV_RD32(par->PGRAPH, 0x0700)) ; in NVSync()
109 static void NVDmaKickoff(struct nvidia_par *par) in NVDmaKickoff() argument
111 if (par->dmaCurrent != par->dmaPut) { in NVDmaKickoff()
112 par->dmaPut = par->dmaCurrent; in NVDmaKickoff()
113 WRITE_PUT(par, par->dmaPut); in NVDmaKickoff()
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H A Dnv_i2c.c31 struct nvidia_par *par = chan->par; in nvidia_gpio_setscl() local
34 val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; in nvidia_gpio_setscl()
41 NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); in nvidia_gpio_setscl()
47 struct nvidia_par *par = chan->par; in nvidia_gpio_setsda() local
50 val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; in nvidia_gpio_setsda()
57 NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); in nvidia_gpio_setsda()
63 struct nvidia_par *par = chan->par; in nvidia_gpio_getscl() local
66 if (NVReadCrtc(par, chan->ddc_base) & 0x04) in nvidia_gpio_getscl()
75 struct nvidia_par *par = chan->par; in nvidia_gpio_getsda() local
78 if (NVReadCrtc(par, chan->ddc_base) & 0x08) in nvidia_gpio_getsda()
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/linux/drivers/staging/fbtft/
H A Dfb_ra8875.c17 static int write_spi(struct fbtft_par *par, void *buf, size_t len) in write_spi() argument
26 fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len, in write_spi()
29 if (!par->spi) { in write_spi()
30 dev_err(par->info->device, in write_spi()
37 return spi_sync(par->spi, &m); in write_spi()
40 static int init_display(struct fbtft_par *par) in init_display() argument
42 gpiod_set_value(par->gpio.dc, 1); in init_display()
44 par->fbtftops.reset(par); in init_display()
46 if ((par->info->var.xres == 320) && (par->info->var.yres == 240)) { in init_display()
48 write_reg(par, 0x88, 0x0A); in init_display()
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H A Dfb_bd663474.c24 static int init_display(struct fbtft_par *par) in init_display() argument
26 par->fbtftops.reset(par); in init_display()
31 write_reg(par, 0x000, 0x0001); /*oscillator 0: stop, 1: operation */ in init_display()
35 write_reg(par, 0x100, 0x0000); /* power supply setup */ in init_display()
36 write_reg(par, 0x101, 0x0000); in init_display()
37 write_reg(par, 0x102, 0x3110); in init_display()
38 write_reg(par, 0x103, 0xe200); in init_display()
39 write_reg(par, 0x110, 0x009d); in init_display()
40 write_reg(par, 0x111, 0x0022); in init_display()
41 write_reg(par, 0x100, 0x0120); in init_display()
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H A Dfb_ili9320.c22 static unsigned int read_devicecode(struct fbtft_par *par) in read_devicecode() argument
26 write_reg(par, 0x0000); in read_devicecode()
27 par->fbtftops.read(par, rxbuf, 4); in read_devicecode()
31 static int init_display(struct fbtft_par *par) in init_display() argument
35 par->fbtftops.reset(par); in init_display()
37 devcode = read_devicecode(par); in init_display()
39 dev_warn(par->info->device, in init_display()
47 write_reg(par, 0x00E5, 0x8000); in init_display()
50 write_reg(par, 0x0000, 0x0001); in init_display()
53 write_reg(par, 0x0001, 0x0100); in init_display()
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H A Dfb_upd161704.c24 static int init_display(struct fbtft_par *par) in init_display() argument
26 par->fbtftops.reset(par); in init_display()
31 write_reg(par, 0x0003, 0x0001); /* Soft reset */ in init_display()
34 write_reg(par, 0x003A, 0x0001); /*Oscillator 0: stop, 1: operation */ in init_display()
38 write_reg(par, 0x0024, 0x007B); /* amplitude setting */ in init_display()
40 write_reg(par, 0x0025, 0x003B); /* amplitude setting */ in init_display()
41 write_reg(par, 0x0026, 0x0034); /* amplitude setting */ in init_display()
43 write_reg(par, 0x0027, 0x0004); /* amplitude setting */ in init_display()
44 write_reg(par, 0x0052, 0x0025); /* circuit setting 1 */ in init_display()
46 write_reg(par, 0x0053, 0x0033); /* circuit setting 2 */ in init_display()
[all …]
H A Dfb_s6d1121.c27 static int init_display(struct fbtft_par *par) in init_display() argument
29 par->fbtftops.reset(par); in init_display()
33 write_reg(par, 0x0011, 0x2004); in init_display()
34 write_reg(par, 0x0013, 0xCC00); in init_display()
35 write_reg(par, 0x0015, 0x2600); in init_display()
36 write_reg(par, 0x0014, 0x252A); in init_display()
37 write_reg(par, 0x0012, 0x0033); in init_display()
38 write_reg(par, 0x0013, 0xCC04); in init_display()
39 write_reg(par, 0x0013, 0xCC06); in init_display()
40 write_reg(par, 0x0013, 0xCC4F); in init_display()
[all …]
H A Dfb_ssd1289.c26 static int init_display(struct fbtft_par *par) in init_display() argument
28 par->fbtftops.reset(par); in init_display()
30 write_reg(par, 0x00, 0x0001); in init_display()
31 write_reg(par, 0x03, 0xA8A4); in init_display()
32 write_reg(par, 0x0C, 0x0000); in init_display()
33 write_reg(par, 0x0D, 0x080C); in init_display()
34 write_reg(par, 0x0E, 0x2B00); in init_display()
35 write_reg(par, 0x1E, 0x00B7); in init_display()
36 write_reg(par, 0x01, in init_display()
37 BIT(13) | (par->bgr << 11) | BIT(9) | (HEIGHT - 1)); in init_display()
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H A Dfb_ssd1306.c32 static int init_display(struct fbtft_par *par) in init_display() argument
34 par->fbtftops.reset(par); in init_display()
36 if (par->gamma.curves[0] == 0) { in init_display()
37 mutex_lock(&par->gamma.lock); in init_display()
38 if (par->info->var.yres == 64) in init_display()
39 par->gamma.curves[0] = 0xCF; in init_display()
41 par->gamma.curves[0] = 0x8F; in init_display()
42 mutex_unlock(&par->gamma.lock); in init_display()
46 write_reg(par, 0xAE); in init_display()
49 write_reg(par, 0xD5); in init_display()
[all …]
H A Dfb_ili9325.c83 static int init_display(struct fbtft_par *par) in init_display() argument
85 par->fbtftops.reset(par); in init_display()
96 write_reg(par, 0x00E3, 0x3008); /* Set internal timing */ in init_display()
97 write_reg(par, 0x00E7, 0x0012); /* Set internal timing */ in init_display()
98 write_reg(par, 0x00EF, 0x1231); /* Set internal timing */ in init_display()
99 write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */ in init_display()
100 write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */ in init_display()
101 write_reg(par, 0x0004, 0x0000); /* Resize register */ in init_display()
102 write_reg(par, 0x0008, 0x0207); /* set the back porch and front porch */ in init_display()
103 write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */ in init_display()
[all …]
H A Dfb_hx8347d.c23 static int init_display(struct fbtft_par *par) in init_display() argument
25 par->fbtftops.reset(par); in init_display()
28 write_reg(par, 0xEA, 0x00); in init_display()
29 write_reg(par, 0xEB, 0x20); in init_display()
30 write_reg(par, 0xEC, 0x0C); in init_display()
31 write_reg(par, 0xED, 0xC4); in init_display()
32 write_reg(par, 0xE8, 0x40); in init_display()
33 write_reg(par, 0xE9, 0x38); in init_display()
34 write_reg(par, 0xF1, 0x01); in init_display()
35 write_reg(par, 0xF2, 0x10); in init_display()
[all …]
H A Dfb_ssd1305.c33 static int init_display(struct fbtft_par *par) in init_display() argument
35 par->fbtftops.reset(par); in init_display()
37 if (par->gamma.curves[0] == 0) { in init_display()
38 mutex_lock(&par->gamma.lock); in init_display()
39 if (par->info->var.yres == 64) in init_display()
40 par->gamma.curves[0] = 0xCF; in init_display()
42 par->gamma.curves[0] = 0x8F; in init_display()
43 mutex_unlock(&par->gamma.lock); in init_display()
47 write_reg(par, 0xAE); in init_display()
50 write_reg(par, 0xD5); in init_display()
[all …]
H A Dfb_ssd1325.c34 static int init_display(struct fbtft_par *par) in init_display() argument
36 par->fbtftops.reset(par); in init_display()
38 write_reg(par, 0xb3); in init_display()
39 write_reg(par, 0xf0); in init_display()
40 write_reg(par, 0xae); in init_display()
41 write_reg(par, 0xa1); in init_display()
42 write_reg(par, 0x00); in init_display()
43 write_reg(par, 0xa8); in init_display()
44 write_reg(par, 0x3f); in init_display()
45 write_reg(par, 0xa0); in init_display()
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H A Dfb_uc1611.c62 static int init_display(struct fbtft_par *par) in init_display() argument
72 par->spi->mode ^= SPI_CS_HIGH; in init_display()
73 ret = spi_setup(par->spi); in init_display()
75 dev_err(par->info->device, in init_display()
81 write_reg(par, 0xE2); in init_display()
84 write_reg(par, 0xE8 | (ratio & 0x03)); in init_display()
87 write_reg(par, 0x81); in init_display()
88 write_reg(par, (gain & 0x03) << 6 | (pot & 0x3F)); in init_display()
91 write_reg(par, 0x24 | (temp & 0x03)); in init_display()
94 write_reg(par, 0x28 | (load & 0x03)); in init_display()
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H A Dfb_ssd1331.c25 static int init_display(struct fbtft_par *par) in init_display() argument
27 par->fbtftops.reset(par); in init_display()
29 write_reg(par, 0xae); /* Display Off */ in init_display()
32 if (par->info->var.rotate == 180) in init_display()
33 write_reg(par, 0xa0, 0x60 | (par->bgr << 2)); in init_display()
35 write_reg(par, 0xa0, 0x72 | (par->bgr << 2)); in init_display()
37 write_reg(par, 0x72); /* RGB colour */ in init_display()
38 write_reg(par, 0xa1, 0x00); /* Set Display Start Line */ in init_display()
39 write_reg(par, 0xa2, 0x00); /* Set Display Offset */ in init_display()
40 write_reg(par, 0xa4); /* NORMALDISPLAY */ in init_display()
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H A Dfb_sh1106.c21 static int init_display(struct fbtft_par *par) in init_display() argument
23 if (!par->info->var.xres || par->info->var.xres > WIDTH || in init_display()
24 !par->info->var.yres || par->info->var.yres > HEIGHT || in init_display()
25 par->info->var.yres % 8) { in init_display()
26 dev_err(par->info->device, "Invalid screen size\n"); in init_display()
30 if (par->info->var.rotate) { in init_display()
31 dev_err(par->info->device, "Display rotation not supported\n"); in init_display()
35 par->fbtftops.reset(par); in init_display()
38 write_reg(par, 0xAE); in init_display()
41 write_reg(par, 0xD5, 0x80); in init_display()
[all …]
/linux/drivers/video/fbdev/riva/
H A Dnv_driver.c46 static inline unsigned char MISCin(struct riva_par *par) in MISCin() argument
48 return (VGA_RD08(par->riva.PVIO, 0x3cc)); in MISCin()
52 riva_is_connected(struct riva_par *par, Bool second) in riva_is_connected() argument
54 volatile U032 __iomem *PRAMDAC = par->riva.PRAMDAC0; in riva_is_connected()
69 NV_WR32(par->riva.PRAMDAC0, 0x0610, 0x94050140); in riva_is_connected()
70 NV_WR32(par->riva.PRAMDAC0, 0x0608, 0x00001000); in riva_is_connected()
76 NV_WR32(par->riva.PRAMDAC0, 0x0608, in riva_is_connected()
77 NV_RD32(par->riva.PRAMDAC0, 0x0608) & 0x0000EFFF); in riva_is_connected()
86 riva_override_CRTC(struct riva_par *par) in riva_override_CRTC() argument
90 par->SecondCRTC ? 1 : 0); in riva_override_CRTC()
[all …]
/linux/drivers/video/fbdev/aty/
H A Dmach64_accel.c40 void aty_reset_engine(struct atyfb_par *par) in aty_reset_engine() argument
44 aty_ld_le32(GEN_TEST_CNTL, par) & in aty_reset_engine()
45 ~(GUI_ENGINE_ENABLE | HWCURSOR_ENABLE), par); in aty_reset_engine()
48 aty_ld_le32(GEN_TEST_CNTL, par) | GUI_ENGINE_ENABLE, par); in aty_reset_engine()
52 aty_ld_le32(BUS_CNTL, par) | BUS_HOST_ERR_ACK | BUS_FIFO_ERR_ACK, par); in aty_reset_engine()
54 par->fifo_space = 0; in aty_reset_engine()
57 static void reset_GTC_3D_engine(const struct atyfb_par *par) in reset_GTC_3D_engine() argument
59 aty_st_le32(SCALE_3D_CNTL, 0xc0, par); in reset_GTC_3D_engine()
61 aty_st_le32(SETUP_CNTL, 0x00, par); in reset_GTC_3D_engine()
63 aty_st_le32(SCALE_3D_CNTL, 0x00, par); in reset_GTC_3D_engine()
[all …]
H A Dmach64_gx.c43 static void aty_dac_waste4(const struct atyfb_par *par) in aty_dac_waste4() argument
45 (void) aty_ld_8(DAC_REGS, par); in aty_dac_waste4()
47 (void) aty_ld_8(DAC_REGS + 2, par); in aty_dac_waste4()
48 (void) aty_ld_8(DAC_REGS + 2, par); in aty_dac_waste4()
49 (void) aty_ld_8(DAC_REGS + 2, par); in aty_dac_waste4()
50 (void) aty_ld_8(DAC_REGS + 2, par); in aty_dac_waste4()
53 static void aty_StrobeClock(const struct atyfb_par *par) in aty_StrobeClock() argument
59 tmp = aty_ld_8(CLOCK_CNTL, par); in aty_StrobeClock()
60 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, tmp | CLOCK_STROBE, par); in aty_StrobeClock()
69 static void aty_st_514(int offset, u8 val, const struct atyfb_par *par) in aty_st_514() argument
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/linux/drivers/video/fbdev/i810/
H A Di810-i2c.c45 struct i810fb_par *par = chan->par; in i810i2c_setscl() local
46 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_setscl()
58 struct i810fb_par *par = chan->par; in i810i2c_setsda() local
59 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_setsda()
71 struct i810fb_par *par = chan->par; in i810i2c_getscl() local
72 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_getscl()
82 struct i810fb_par *par = chan->par; in i810i2c_getsda() local
83 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_getsda()
97 chan->adapter.dev.parent = &chan->par->dev->dev; in i810_setup_i2c_bus()
116 dev_dbg(&chan->par->dev->dev, "I2C bus %s registered.\n",name); in i810_setup_i2c_bus()
[all …]
/linux/drivers/video/fbdev/
H A Dpmagb-b-fb.c69 static inline void sfb_write(struct pmagbbfb_par *par, unsigned int reg, u32 v) in sfb_write() argument
71 writel(v, par->sfb + reg / 4); in sfb_write()
74 static inline u32 sfb_read(struct pmagbbfb_par *par, unsigned int reg) in sfb_read() argument
76 return readl(par->sfb + reg / 4); in sfb_read()
79 static inline void dac_write(struct pmagbbfb_par *par, unsigned int reg, u8 v) in dac_write() argument
81 writeb(v, par->dac + reg / 4); in dac_write()
84 static inline u8 dac_read(struct pmagbbfb_par *par, unsigned int reg) in dac_read() argument
86 return readb(par->dac + reg / 4); in dac_read()
89 static inline void gp0_write(struct pmagbbfb_par *par, u32 v) in gp0_write() argument
91 writel(v, par->mmio + PMAGB_B_GP0); in gp0_write()
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H A Dimsttfb.c424 getclkMHz(struct imstt_par *par) in getclkMHz() argument
428 clk_m = par->init.pclk_m; in getclkMHz()
429 clk_n = par->init.pclk_n; in getclkMHz()
430 clk_p = par->init.pclk_p; in getclkMHz()
436 setclkMHz(struct imstt_par *par, __u32 MHz) in setclkMHz() argument
462 par->init.pclk_m = clk_m; in setclkMHz()
463 par->init.pclk_n = clk_n; in setclkMHz()
464 par->init.pclk_p = 0; in setclkMHz()
468 compute_imstt_regvals_ibm(struct imstt_par *par, int xres, int yres) in compute_imstt_regvals_ibm() argument
470 struct imstt_regvals *init = &par->init; in compute_imstt_regvals_ibm()
[all …]
/linux/drivers/video/fbdev/mb862xx/
H A Dmb862xxfbdrv.c75 struct mb862xxfb_par *par = info->par; in mb862xxfb_setcolreg() local
84 par->pseudo_palette[regno] = val; in mb862xxfb_setcolreg()
197 struct mb862xxfb_par *par = fbi->par; in mb862xxfb_set_par() local
200 dev_dbg(par->dev, "%s\n", __func__); in mb862xxfb_set_par()
201 if (par->type == BT_CORALP) in mb862xxfb_set_par()
204 if (par->pre_init) in mb862xxfb_set_par()
213 sc = par->refclk / (1000000 / fbi->var.pixclock) - 1; in mb862xxfb_set_par()
218 dev_dbg(par->dev, "SC 0x%lx\n", sc); in mb862xxfb_set_par()
267 struct mb862xxfb_par *par = info->par; in mb862xxfb_pan() local
280 struct mb862xxfb_par *par = fbi->par; in mb862xxfb_blank() local
[all …]

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