| /linux/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_pm4_headers.h | 69 uint32_t page_table_base:28; member
118 uint32_t page_table_base:28; member
|
| H A D | kfd_packet_manager_vi.c | 56 packet->bitfields3.page_table_base = qpd->page_table_base; in pm_map_process_vi()
|
| H A D | kfd_packet_manager_v9.c | 36 uint64_t vm_page_table_base_addr = qpd->page_table_base; in pm_map_process_v9()
93 uint64_t vm_page_table_base_addr = qpd->page_table_base; in pm_map_process_aldebaran()
|
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfxhub_v1_2.c | 44 uint64_t page_table_base, in gfxhub_v1_2_xcc_setup_vm_pt_regs() argument
55 lower_32_bits(page_table_base)); in gfxhub_v1_2_xcc_setup_vm_pt_regs()
60 upper_32_bits(page_table_base)); in gfxhub_v1_2_xcc_setup_vm_pt_regs()
66 uint64_t page_table_base) in gfxhub_v1_2_setup_vm_pt_regs() argument
71 gfxhub_v1_2_xcc_setup_vm_pt_regs(adev, vmid, page_table_base, xcc_mask); in gfxhub_v1_2_setup_vm_pt_regs()
|
| H A D | amdgpu_gfxhub.h | 30 uint64_t page_table_base);
|
| H A D | amdgpu_mmhub.h | 63 uint64_t page_table_base);
|
| H A D | gfxhub_v1_0.c | 41 uint64_t page_table_base) in gfxhub_v1_0_setup_vm_pt_regs() argument
47 lower_32_bits(page_table_base)); in gfxhub_v1_0_setup_vm_pt_regs()
51 upper_32_bits(page_table_base)); in gfxhub_v1_0_setup_vm_pt_regs()
|
| H A D | gfxhub_v3_0_3.c | 123 uint64_t page_table_base) in gfxhub_v3_0_3_setup_vm_pt_regs() argument
129 lower_32_bits(page_table_base)); in gfxhub_v3_0_3_setup_vm_pt_regs()
133 upper_32_bits(page_table_base)); in gfxhub_v3_0_3_setup_vm_pt_regs()
|
| H A D | gfxhub_v2_0.c | 121 uint64_t page_table_base) in gfxhub_v2_0_setup_vm_pt_regs() argument
127 lower_32_bits(page_table_base)); in gfxhub_v2_0_setup_vm_pt_regs()
131 upper_32_bits(page_table_base)); in gfxhub_v2_0_setup_vm_pt_regs()
|
| H A D | gfxhub_v11_5_0.c | 125 uint64_t page_table_base) in gfxhub_v11_5_0_setup_vm_pt_regs() argument
131 lower_32_bits(page_table_base)); in gfxhub_v11_5_0_setup_vm_pt_regs()
135 upper_32_bits(page_table_base)); in gfxhub_v11_5_0_setup_vm_pt_regs()
|
| H A D | mmhub_v3_0_2.c | 130 uint64_t page_table_base) in mmhub_v3_0_2_setup_vm_pt_regs() argument
136 lower_32_bits(page_table_base)); in mmhub_v3_0_2_setup_vm_pt_regs()
140 upper_32_bits(page_table_base)); in mmhub_v3_0_2_setup_vm_pt_regs()
|
| H A D | gfxhub_v3_0.c | 120 uint64_t page_table_base) in gfxhub_v3_0_setup_vm_pt_regs() argument
126 lower_32_bits(page_table_base)); in gfxhub_v3_0_setup_vm_pt_regs()
130 upper_32_bits(page_table_base)); in gfxhub_v3_0_setup_vm_pt_regs()
|
| H A D | gfxhub_v12_0.c | 128 uint64_t page_table_base) in gfxhub_v12_0_setup_vm_pt_regs() argument
134 lower_32_bits(page_table_base)); in gfxhub_v12_0_setup_vm_pt_regs()
138 upper_32_bits(page_table_base)); in gfxhub_v12_0_setup_vm_pt_regs()
|
| H A D | mmhub_v3_0_1.c | 139 uint64_t page_table_base) in mmhub_v3_0_1_setup_vm_pt_regs() argument
145 lower_32_bits(page_table_base)); in mmhub_v3_0_1_setup_vm_pt_regs()
149 upper_32_bits(page_table_base)); in mmhub_v3_0_1_setup_vm_pt_regs()
|
| H A D | mmhub_v3_0.c | 137 uint64_t page_table_base) in mmhub_v3_0_setup_vm_pt_regs() argument
143 lower_32_bits(page_table_base)); in mmhub_v3_0_setup_vm_pt_regs()
147 upper_32_bits(page_table_base)); in mmhub_v3_0_setup_vm_pt_regs()
|
| H A D | mmhub_v2_3.c | 122 uint64_t page_table_base) in mmhub_v2_3_setup_vm_pt_regs() argument
127 hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base)); in mmhub_v2_3_setup_vm_pt_regs()
130 hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base)); in mmhub_v2_3_setup_vm_pt_regs()
|
| H A D | mmhub_v2_0.c | 188 uint64_t page_table_base) in mmhub_v2_0_setup_vm_pt_regs() argument
194 lower_32_bits(page_table_base)); in mmhub_v2_0_setup_vm_pt_regs()
198 upper_32_bits(page_table_base)); in mmhub_v2_0_setup_vm_pt_regs()
|
| H A D | mmhub_v3_3.c | 134 uint64_t page_table_base) in mmhub_v3_3_setup_vm_pt_regs() argument
140 lower_32_bits(page_table_base)); in mmhub_v3_3_setup_vm_pt_regs()
144 upper_32_bits(page_table_base)); in mmhub_v3_3_setup_vm_pt_regs()
|
| H A D | mmhub_v4_1_0.c | 137 uint32_t vmid, uint64_t page_table_base) in mmhub_v4_1_0_setup_vm_pt_regs() argument
143 lower_32_bits(page_table_base)); in mmhub_v4_1_0_setup_vm_pt_regs()
147 upper_32_bits(page_table_base)); in mmhub_v4_1_0_setup_vm_pt_regs()
|
| H A D | mmhub_v1_0.c | 55 uint64_t page_table_base) in mmhub_v1_0_setup_vm_pt_regs() argument
61 lower_32_bits(page_table_base)); in mmhub_v1_0_setup_vm_pt_regs()
65 upper_32_bits(page_table_base)); in mmhub_v1_0_setup_vm_pt_regs()
|
| H A D | mmhub_v1_8.c | 56 uint64_t page_table_base) in mmhub_v1_8_setup_vm_pt_regs() argument
68 lower_32_bits(page_table_base)); in mmhub_v1_8_setup_vm_pt_regs()
73 upper_32_bits(page_table_base)); in mmhub_v1_8_setup_vm_pt_regs()
|
| H A D | amdgpu_amdkfd_gfx_v9.h | 54 uint32_t vmid, uint64_t page_table_base);
|
| H A D | amdgpu_amdkfd_gfx_v7.c | 540 uint32_t vmid, uint64_t page_table_base) in set_vm_context_page_table_base() argument
547 lower_32_bits(page_table_base)); in set_vm_context_page_table_base()
|
| H A D | gfxhub_v2_1.c | 124 uint64_t page_table_base) in gfxhub_v2_1_setup_vm_pt_regs() argument
130 lower_32_bits(page_table_base)); in gfxhub_v2_1_setup_vm_pt_regs()
134 upper_32_bits(page_table_base)); in gfxhub_v2_1_setup_vm_pt_regs()
|
| H A D | amdgpu_amdkfd_gfx_v8.c | 575 uint32_t vmid, uint64_t page_table_base) in set_vm_context_page_table_base() argument
582 lower_32_bits(page_table_base)); in set_vm_context_page_table_base()
|