| /linux/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_pm4_headers.h | 69 uint32_t page_table_base:28; member
118 uint32_t page_table_base:28; member
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| H A D | kfd_pm4_headers_vi.h | 164 uint32_t page_table_base:28; member
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| H A D | kfd_device_queue_manager.c | 223 queue_input.page_table_base_addr = qpd->page_table_base; in add_queue_mes()
701 /* qpd->page_table_base is set earlier when register_process() in flush_texture_cache_nocpsch()
706 qpd->page_table_base); in flush_texture_cache_nocpsch()
1529 qpd->page_table_base = pd_base; in restore_process_queues_nocpsch()
1536 qpd->page_table_base); in restore_process_queues_nocpsch()
1613 qpd->page_table_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); in restore_process_queues_cpsch()
1614 pr_debug("Updated PD address to 0x%llx\n", qpd->page_table_base); in restore_process_queues_cpsch()
1675 qpd->page_table_base = pd_base; in unregister_process()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_gfxhub.h | 30 uint64_t page_table_base);
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| H A D | gfxhub_v1_2.c | 44 uint64_t page_table_base, in gfxhub_v1_2_xcc_setup_vm_pt_regs() argument
55 lower_32_bits(page_table_base)); in gfxhub_v1_2_xcc_setup_vm_pt_regs()
60 upper_32_bits(page_table_base)); in gfxhub_v1_2_xcc_setup_vm_pt_regs()
66 uint64_t page_table_base) in gfxhub_v1_2_setup_vm_pt_regs() argument
71 gfxhub_v1_2_xcc_setup_vm_pt_regs(adev, vmid, page_table_base, xcc_mask); in gfxhub_v1_2_setup_vm_pt_regs()
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| H A D | gfxhub_v12_1.c | 62 uint64_t page_table_base, in gfxhub_v12_1_xcc_setup_vm_pt_regs() argument
73 lower_32_bits(page_table_base)); in gfxhub_v12_1_xcc_setup_vm_pt_regs()
78 upper_32_bits(page_table_base)); in gfxhub_v12_1_xcc_setup_vm_pt_regs()
84 uint64_t page_table_base) in gfxhub_v12_1_setup_vm_pt_regs() argument
89 gfxhub_v12_1_xcc_setup_vm_pt_regs(adev, vmid, page_table_base, in gfxhub_v12_1_setup_vm_pt_regs()
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| H A D | gfxhub_v2_0.c | 121 uint64_t page_table_base) in gfxhub_v2_0_setup_vm_pt_regs() argument
127 lower_32_bits(page_table_base)); in gfxhub_v2_0_setup_vm_pt_regs()
131 upper_32_bits(page_table_base)); in gfxhub_v2_0_setup_vm_pt_regs()
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| H A D | gfxhub_v1_0.c | 41 uint64_t page_table_base) in gfxhub_v1_0_setup_vm_pt_regs() argument
47 lower_32_bits(page_table_base)); in gfxhub_v1_0_setup_vm_pt_regs()
51 upper_32_bits(page_table_base)); in gfxhub_v1_0_setup_vm_pt_regs()
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| H A D | mmhub_v2_0.c | 173 uint64_t page_table_base) in mmhub_v2_0_setup_vm_pt_regs() argument
179 lower_32_bits(page_table_base)); in mmhub_v2_0_setup_vm_pt_regs()
183 upper_32_bits(page_table_base)); in mmhub_v2_0_setup_vm_pt_regs()
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| H A D | mmhub_v2_3.c | 113 uint64_t page_table_base) in mmhub_v2_3_setup_vm_pt_regs() argument
118 hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base)); in mmhub_v2_3_setup_vm_pt_regs()
121 hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base)); in mmhub_v2_3_setup_vm_pt_regs()
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| H A D | gfxhub_v2_1.c | 124 uint64_t page_table_base) in gfxhub_v2_1_setup_vm_pt_regs() argument
130 lower_32_bits(page_table_base)); in gfxhub_v2_1_setup_vm_pt_regs()
134 upper_32_bits(page_table_base)); in gfxhub_v2_1_setup_vm_pt_regs()
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| H A D | amdgpu_amdkfd_gfx_v7.c | 540 uint32_t vmid, uint64_t page_table_base) in set_vm_context_page_table_base() argument
547 lower_32_bits(page_table_base)); in set_vm_context_page_table_base()
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| H A D | mmhub_v1_0.c | 55 uint64_t page_table_base) in mmhub_v1_0_setup_vm_pt_regs() argument
61 lower_32_bits(page_table_base)); in mmhub_v1_0_setup_vm_pt_regs()
65 upper_32_bits(page_table_base)); in mmhub_v1_0_setup_vm_pt_regs()
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| H A D | amdgpu_amdkfd_gfx_v8.c | 575 uint32_t vmid, uint64_t page_table_base) in set_vm_context_page_table_base() argument
582 lower_32_bits(page_table_base)); in set_vm_context_page_table_base()
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| H A D | amdgpu_amdkfd_gfx_v10_3.c | 626 uint32_t vmid, uint64_t page_table_base) in set_vm_context_page_table_base_v10_3() argument
629 adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); in set_vm_context_page_table_base_v10_3()
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| H A D | amdgpu_amdkfd_gfx_v9.c | 914 uint32_t vmid, uint64_t page_table_base) in kgd_gfx_v9_set_vm_context_page_table_base() argument
922 adev->mmhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); in kgd_gfx_v9_set_vm_context_page_table_base()
924 adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); in kgd_gfx_v9_set_vm_context_page_table_base()
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| H A D | amdgpu_amdkfd_gfx_v11.c | 600 uint32_t vmid, uint64_t page_table_base) in set_vm_context_page_table_base_v11() argument
609 adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); in set_vm_context_page_table_base_v11()
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| H A D | amdgpu_amdkfd_gfx_v10.c | 702 uint32_t vmid, uint64_t page_table_base) in set_vm_context_page_table_base() argument
711 adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); in set_vm_context_page_table_base()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm.c | 326 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; in mmhub_read_system_context() local
375 page_table_base.high_part = upper_32_bits(pt_base); in mmhub_read_system_context()
376 page_table_base.low_part = lower_32_bits(pt_base); in mmhub_read_system_context()
391 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; in mmhub_read_system_context()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 1033 plane->address.page_table_base.quad_part == 0 && in dcn30_apply_idle_power_optimizations()
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