| /linux/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_pm4_headers.h | 69 uint32_t page_table_base:28; member
118 uint32_t page_table_base:28; member
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| H A D | kfd_pm4_headers_vi.h | 164 uint32_t page_table_base:28; member
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| H A D | kfd_device_queue_manager.c | 217 queue_input.page_table_base_addr = qpd->page_table_base; in add_queue_mes()
573 qpd->page_table_base); in allocate_vmid()
1279 qpd->page_table_base = pd_base; in restore_process_queues_nocpsch()
1286 qpd->page_table_base); in restore_process_queues_nocpsch()
1363 qpd->page_table_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv); in restore_process_queues_cpsch()
1364 pr_debug("Updated PD address to 0x%llx\n", qpd->page_table_base); in restore_process_queues_cpsch()
1418 qpd->page_table_base = pd_base; in register_process()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_gfxhub.h | 30 uint64_t page_table_base);
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| H A D | amdgpu_mmhub.h | 63 uint64_t page_table_base);
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| H A D | gfxhub_v3_0_3.c | 123 uint64_t page_table_base) in gfxhub_v3_0_3_setup_vm_pt_regs() argument
129 lower_32_bits(page_table_base)); in gfxhub_v3_0_3_setup_vm_pt_regs()
133 upper_32_bits(page_table_base)); in gfxhub_v3_0_3_setup_vm_pt_regs()
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| H A D | gfxhub_v2_0.c | 121 uint64_t page_table_base) in gfxhub_v2_0_setup_vm_pt_regs() argument
127 lower_32_bits(page_table_base)); in gfxhub_v2_0_setup_vm_pt_regs()
131 upper_32_bits(page_table_base)); in gfxhub_v2_0_setup_vm_pt_regs()
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| H A D | mmhub_v4_2_0.c | 99 uint64_t page_table_base, in mmhub_v4_2_0_mid_setup_vm_pt_regs() argument
110 lower_32_bits(page_table_base)); in mmhub_v4_2_0_mid_setup_vm_pt_regs()
115 upper_32_bits(page_table_base)); in mmhub_v4_2_0_mid_setup_vm_pt_regs()
121 uint64_t page_table_base) in mmhub_v4_2_0_setup_vm_pt_regs() argument
127 page_table_base, in mmhub_v4_2_0_setup_vm_pt_regs()
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| H A D | gfxhub_v11_5_0.c | 125 uint64_t page_table_base) in gfxhub_v11_5_0_setup_vm_pt_regs() argument
131 lower_32_bits(page_table_base)); in gfxhub_v11_5_0_setup_vm_pt_regs()
135 upper_32_bits(page_table_base)); in gfxhub_v11_5_0_setup_vm_pt_regs()
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| H A D | mmhub_v3_0_2.c | 130 uint64_t page_table_base) in mmhub_v3_0_2_setup_vm_pt_regs() argument
136 lower_32_bits(page_table_base)); in mmhub_v3_0_2_setup_vm_pt_regs()
140 upper_32_bits(page_table_base)); in mmhub_v3_0_2_setup_vm_pt_regs()
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| H A D | gfxhub_v3_0.c | 120 uint64_t page_table_base) in gfxhub_v3_0_setup_vm_pt_regs() argument
126 lower_32_bits(page_table_base)); in gfxhub_v3_0_setup_vm_pt_regs()
130 upper_32_bits(page_table_base)); in gfxhub_v3_0_setup_vm_pt_regs()
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| H A D | gfxhub_v12_0.c | 128 uint64_t page_table_base) in gfxhub_v12_0_setup_vm_pt_regs() argument
134 lower_32_bits(page_table_base)); in gfxhub_v12_0_setup_vm_pt_regs()
138 upper_32_bits(page_table_base)); in gfxhub_v12_0_setup_vm_pt_regs()
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| H A D | mmhub_v3_0_1.c | 146 uint64_t page_table_base) in mmhub_v3_0_1_setup_vm_pt_regs() argument
152 lower_32_bits(page_table_base)); in mmhub_v3_0_1_setup_vm_pt_regs()
156 upper_32_bits(page_table_base)); in mmhub_v3_0_1_setup_vm_pt_regs()
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| H A D | mmhub_v3_0.c | 137 uint64_t page_table_base) in mmhub_v3_0_setup_vm_pt_regs() argument
143 lower_32_bits(page_table_base)); in mmhub_v3_0_setup_vm_pt_regs()
147 upper_32_bits(page_table_base)); in mmhub_v3_0_setup_vm_pt_regs()
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| H A D | mmhub_v2_3.c | 122 uint64_t page_table_base) in mmhub_v2_3_setup_vm_pt_regs() argument
127 hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base)); in mmhub_v2_3_setup_vm_pt_regs()
130 hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base)); in mmhub_v2_3_setup_vm_pt_regs()
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| H A D | mmhub_v2_0.c | 188 uint64_t page_table_base) in mmhub_v2_0_setup_vm_pt_regs() argument
194 lower_32_bits(page_table_base)); in mmhub_v2_0_setup_vm_pt_regs()
198 upper_32_bits(page_table_base)); in mmhub_v2_0_setup_vm_pt_regs()
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| H A D | mmhub_v4_1_0.c | 129 uint32_t vmid, uint64_t page_table_base) in mmhub_v4_1_0_setup_vm_pt_regs() argument
135 lower_32_bits(page_table_base)); in mmhub_v4_1_0_setup_vm_pt_regs()
139 upper_32_bits(page_table_base)); in mmhub_v4_1_0_setup_vm_pt_regs()
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| H A D | amdgpu_amdkfd_gfx_v7.c | 540 uint32_t vmid, uint64_t page_table_base) in set_vm_context_page_table_base() argument
547 lower_32_bits(page_table_base)); in set_vm_context_page_table_base()
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| H A D | mmhub_v1_0.c | 55 uint64_t page_table_base) in mmhub_v1_0_setup_vm_pt_regs() argument
61 lower_32_bits(page_table_base)); in mmhub_v1_0_setup_vm_pt_regs()
65 upper_32_bits(page_table_base)); in mmhub_v1_0_setup_vm_pt_regs()
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| H A D | amdgpu_amdkfd_gfx_v8.c | 575 uint32_t vmid, uint64_t page_table_base) in set_vm_context_page_table_base() argument
582 lower_32_bits(page_table_base)); in set_vm_context_page_table_base()
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| H A D | amdgpu_amdkfd_gfx_v10_3.c | 626 uint32_t vmid, uint64_t page_table_base) in set_vm_context_page_table_base_v10_3() argument
629 adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); in set_vm_context_page_table_base_v10_3()
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| H A D | amdgpu_amdkfd_gfx_v9.c | 914 uint32_t vmid, uint64_t page_table_base) in kgd_gfx_v9_set_vm_context_page_table_base() argument
922 adev->mmhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); in kgd_gfx_v9_set_vm_context_page_table_base()
924 adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); in kgd_gfx_v9_set_vm_context_page_table_base()
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| H A D | amdgpu_amdkfd_gfx_v11.c | 599 uint32_t vmid, uint64_t page_table_base) in set_vm_context_page_table_base_v11() argument
608 adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); in set_vm_context_page_table_base_v11()
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| H A D | amdgpu_amdkfd_gfx_v10.c | 702 uint32_t vmid, uint64_t page_table_base) in set_vm_context_page_table_base() argument
711 adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); in set_vm_context_page_table_base()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_hw_types.h | 125 union large_integer page_table_base; member
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