| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| H A D | dcn314_dccg.c | 61 uint32_t otg_inst, in dccg314_get_pixel_rate_div() argument
71 switch (otg_inst) { in dccg314_get_pixel_rate_div()
103 uint32_t otg_inst, in dccg314_set_pixel_rate_div() argument
118 dccg314_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2); in dccg314_set_pixel_rate_div()
122 switch (otg_inst) { in dccg314_set_pixel_rate_div()
152 uint32_t otg_inst) in dccg314_set_dtbclk_p_src() argument
161 switch (otg_inst) { in dccg314_set_dtbclk_p_src()
221 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); in dccg314_set_dtbclk_dto()
222 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase); in dccg314_set_dtbclk_dto()
224 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], in dccg314_set_dtbclk_dto()
[all …]
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| H A D | dcn314_dccg.h | 211 int otg_inst,
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
| H A D | dcn32_dccg.c | 61 uint32_t otg_inst, in dccg32_get_pixel_rate_div() argument
71 switch (otg_inst) { in dccg32_get_pixel_rate_div()
103 uint32_t otg_inst, in dccg32_set_pixel_rate_div() argument
118 dccg32_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2); in dccg32_set_pixel_rate_div()
122 switch (otg_inst) { in dccg32_set_pixel_rate_div()
152 uint32_t otg_inst) in dccg32_set_dtbclk_p_src() argument
160 switch (otg_inst) { in dccg32_set_dtbclk_p_src()
220 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); in dccg32_set_dtbclk_dto()
221 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase); in dccg32_set_dtbclk_dto()
223 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], in dccg32_set_dtbclk_dto()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| H A D | dcn20_dccg.c | 109 uint32_t otg_inst) in dccg2_otg_add_pixel() argument
113 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_add_pixel()
114 OTG_ADD_PIXEL[otg_inst], 0, in dccg2_otg_add_pixel()
115 OTG_DROP_PIXEL[otg_inst], 0); in dccg2_otg_add_pixel()
116 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_add_pixel()
117 OTG_ADD_PIXEL[otg_inst], 1); in dccg2_otg_add_pixel()
121 uint32_t otg_inst) in dccg2_otg_drop_pixel() argument
125 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_drop_pixel()
126 OTG_ADD_PIXEL[otg_inst], 0, in dccg2_otg_drop_pixel()
127 OTG_DROP_PIXEL[otg_inst], 0); in dccg2_otg_drop_pixel()
[all …]
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| H A D | dcn20_dccg.h | 518 uint32_t otg_inst);
520 uint32_t otg_inst);
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| H A D | dcn35_dccg.c | 1227 uint32_t otg_inst, in dccg35_get_pixel_rate_div() argument
1237 switch (otg_inst) { in dccg35_get_pixel_rate_div()
1269 uint32_t otg_inst, in dccg35_set_pixel_rate_div() argument
1285 dccg35_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2); in dccg35_set_pixel_rate_div()
1289 switch (otg_inst) { in dccg35_set_pixel_rate_div()
1314 if (otg_inst < 4) in dccg35_set_pixel_rate_div()
1321 uint32_t otg_inst) in dccg35_set_dtbclk_p_src() argument
1329 switch (otg_inst) { in dccg35_set_dtbclk_p_src()
1385 switch (params->otg_inst) { in dccg35_set_dtbclk_dto()
1404 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); in dccg35_set_dtbclk_dto()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/ |
| H A D | dcn401_dccg.c | 122 uint32_t otg_inst, in dccg401_get_pixel_rate_div() argument
129 switch (otg_inst) { in dccg401_get_pixel_rate_div()
160 uint32_t otg_inst, in dccg401_set_pixel_rate_div() argument
174 dccg401_get_pixel_rate_div(dccg, otg_inst, &cur_tmds_div, &dp_dto_int); in dccg401_set_pixel_rate_div()
181 switch (otg_inst) { in dccg401_set_pixel_rate_div()
216 uint32_t otg_inst) in dccg401_set_dtbclk_p_src() argument
224 switch (otg_inst) { in dccg401_set_dtbclk_p_src()
365 uint32_t otg_inst) in dccg401_otg_add_pixel() argument
369 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg401_otg_add_pixel()
370 OTG_ADD_PIXEL[otg_inst], 1); in dccg401_otg_add_pixel()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/ |
| H A D | dcn21_hwseq.c | 139 bool dcn21_dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, in dcn21_dmub_abm_set_pipe() argument
149 cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst; in dcn21_dmub_abm_set_pipe()
181 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable() local
198 abm->funcs->set_pipe_ex(abm, otg_inst, SET_ABM_PIPE_IMMEDIATELY_DISABLE, in dcn21_set_abm_immediate_disable()
202 otg_inst, in dcn21_set_abm_immediate_disable()
217 uint32_t otg_inst; in dcn21_set_pipe() local
222 otg_inst = tg->inst; in dcn21_set_pipe()
231 otg_inst, in dcn21_set_pipe()
236 dcn21_dmub_abm_set_pipe(abm, otg_inst, in dcn21_set_pipe()
250 uint32_t otg_inst; in dcn21_set_backlight_level() local
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| H A D | dcn31_dccg.c | 98 static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst) in dccg31_enable_dpstreamclk() argument
103 switch (otg_inst) { in dccg31_enable_dpstreamclk()
130 static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst) in dccg31_disable_dpstreamclk() argument
139 switch (otg_inst) { in dccg31_disable_dpstreamclk()
165 int otg_inst, in dccg31_set_dpstreamclk() argument
169 dccg31_disable_dpstreamclk(dccg, otg_inst); in dccg31_set_dpstreamclk()
171 dccg31_enable_dpstreamclk(dccg, otg_inst); in dccg31_set_dpstreamclk()
581 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], in dccg31_set_dtbclk_dto()
582 DTBCLK_DTO_DIV[params->otg_inst], dtbdto_div); in dccg31_set_dtbclk_dto()
584 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); in dccg31_set_dtbclk_dto()
[all …]
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| H A D | dcn31_dccg.h | 219 int otg_inst,
228 uint32_t otg_inst);
232 uint32_t otg_inst);
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | dccg.h | 60 int otg_inst; member
205 int otg_inst; member
223 uint32_t otg_inst);
225 uint32_t otg_inst);
239 int otg_inst,
297 uint32_t otg_inst,
302 uint32_t otg_inst,
309 int otg_inst,
335 uint32_t otg_inst);
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| H A D | abm.h | 59 bool (*set_abm_pause)(struct abm *abm, bool pause, unsigned int panel_inst, unsigned int otg_inst);
65 unsigned int otg_inst,
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| H A D | dwb.h | 170 int otg_inst; member
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dmub_abm.c | 155 uint32_t otg_inst, in dmub_abm_set_pipe_ex() argument
166 ret = dmub_abm_set_pipe(abm, otg_inst, option, panel_inst, pwrseq_inst); in dmub_abm_set_pipe_ex()
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| H A D | dmub_abm_lcd.h | 47 bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, uint32_t option, uint32_t panel_inst, ui…
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| H A D | dmub_replay.c | 158 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; in dmub_replay_copy_settings()
160 copy_settings_data->otg_inst = 0; in dmub_replay_copy_settings()
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| H A D | dmub_psr.c | 352 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; in dmub_psr_copy_settings()
354 copy_settings_data->otg_inst = 0; in dmub_psr_copy_settings()
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| /linux/drivers/gpu/drm/amd/display/dmub/inc/ |
| H A D | dmub_cmd.h | 1670 uint32_t otg_inst: 3; member
2303 uint8_t otg_inst; member
2619 uint8_t otg_inst; member
2651 uint8_t otg_inst; member
3666 uint8_t otg_inst; member
3994 uint8_t otg_inst; member
4145 uint8_t otg_inst; member
4476 uint8_t otg_inst; member
4613 uint8_t otg_inst; member
5059 uint8_t otg_inst; member
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dm_cp_psp.h | 35 uint8_t otg_inst; member
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_crtc.c | 84 if (acrtc->otg_inst == -1) in amdgpu_dm_crtc_set_vupdate_irq()
87 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; in amdgpu_dm_crtc_set_vupdate_irq()
763 acrtc->otg_inst = -1; in amdgpu_dm_crtc_init()
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| H A D | amdgpu_dm_irq.c | 730 if (acrtc->otg_inst == -1) in dm_irq_state()
733 irq_source = dal_irq_type + acrtc->otg_inst; in dm_irq_state()
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| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_panel_replay.c | 313 cmd.pr_copy_settings.data.otg_inst = pipe_ctx->stream_res.tg->inst; in dp_pr_copy_settings()
315 cmd.pr_copy_settings.data.otg_inst = 0; in dp_pr_copy_settings()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/ |
| H A D | dcn31_hwseq.c | 712 uint32_t otg_inst; in dcn31_set_backlight_level() local
717 otg_inst = tg->inst; in dcn31_set_backlight_level()
720 otg_inst, in dcn31_set_backlight_level()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_lib.c | 240 dml_print("DML PARAMS: otg_inst = %d\n", pipe_dest->otg_inst); in dml_log_pipe_params()
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| H A D | display_mode_structs.h | 530 unsigned char otg_inst; member
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