| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| H A D | dcn314_dccg.c | 61 uint32_t otg_inst, in dccg314_get_pixel_rate_div() argument
71 switch (otg_inst) { in dccg314_get_pixel_rate_div()
103 uint32_t otg_inst, in dccg314_set_pixel_rate_div() argument
118 dccg314_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2); in dccg314_set_pixel_rate_div()
122 switch (otg_inst) { in dccg314_set_pixel_rate_div()
152 uint32_t otg_inst) in dccg314_set_dtbclk_p_src() argument
161 switch (otg_inst) { in dccg314_set_dtbclk_p_src()
221 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); in dccg314_set_dtbclk_dto()
222 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase); in dccg314_set_dtbclk_dto()
224 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], in dccg314_set_dtbclk_dto()
253 dccg314_set_dpstreamclk(struct dccg * dccg,enum streamclk_source src,int otg_inst,int dp_hpo_inst) dccg314_set_dpstreamclk() argument
291 int otg_inst; dccg314_init() local
318 dccg314_set_valid_pixel_rate(struct dccg * dccg,int ref_dtbclk_khz,int otg_inst,int pixclk_khz) dccg314_set_valid_pixel_rate() argument
[all...] |
| H A D | dcn314_dccg.h | 211 int otg_inst,
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| H A D | dcn20_dccg.c | 109 uint32_t otg_inst) in dccg2_otg_add_pixel() argument
113 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_add_pixel()
114 OTG_ADD_PIXEL[otg_inst], 0, in dccg2_otg_add_pixel()
115 OTG_DROP_PIXEL[otg_inst], 0); in dccg2_otg_add_pixel()
116 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_add_pixel()
117 OTG_ADD_PIXEL[otg_inst], 1); in dccg2_otg_add_pixel()
121 uint32_t otg_inst) in dccg2_otg_drop_pixel() argument
125 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_drop_pixel()
126 OTG_ADD_PIXEL[otg_inst], 0, in dccg2_otg_drop_pixel()
127 OTG_DROP_PIXEL[otg_inst], 0); in dccg2_otg_drop_pixel()
[all …]
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| H A D | dcn20_dccg.h | 532 uint32_t otg_inst);
534 uint32_t otg_inst);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/ |
| H A D | dcn21_hwseq.c | 139 bool dcn21_dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, in dcn21_dmub_abm_set_pipe() argument
149 cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = (uint8_t)otg_inst; in dcn21_dmub_abm_set_pipe()
181 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable() local
198 abm->funcs->set_pipe_ex(abm, otg_inst, SET_ABM_PIPE_IMMEDIATELY_DISABLE, in dcn21_set_abm_immediate_disable()
202 otg_inst, in dcn21_set_abm_immediate_disable()
217 uint32_t otg_inst; in dcn21_set_pipe() local
222 otg_inst = tg->inst; in dcn21_set_pipe()
231 otg_inst, in dcn21_set_pipe()
236 dcn21_dmub_abm_set_pipe(abm, otg_inst, in dcn21_set_pipe()
250 uint32_t otg_inst; dcn21_set_backlight_level() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | dccg.h | 60 int otg_inst; member
205 int otg_inst; member
223 uint32_t otg_inst);
225 uint32_t otg_inst);
236 uint32_t otg_inst);
249 int otg_inst,
307 uint32_t otg_inst,
312 uint32_t otg_inst,
319 int otg_inst,
345 uint32_t otg_inst);
[all...] |
| H A D | abm.h | 59 bool (*set_abm_pause)(struct abm *abm, bool pause, unsigned int panel_inst, unsigned int otg_inst);
65 unsigned int otg_inst,
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| H A D | dwb.h | 170 int otg_inst; member
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| H A D | dcn31_dccg.h | 217 uint32_t otg_inst);
232 int otg_inst,
241 uint32_t otg_inst);
245 uint32_t otg_inst);
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dm_cp_psp.h | 35 uint8_t otg_inst; member
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dmub_abm_lcd.h | 47 bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, uint32_t option, uint32_t panel_inst, ui…
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| H A D | dmub_psr.c | 352 copy_settings_data->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; in dmub_psr_copy_settings()
354 copy_settings_data->otg_inst = 0; in dmub_psr_copy_settings()
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| H A D | dce_clock_source.c | 1086 dto_params.otg_inst = inst; in dcn401_program_pix_clk()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_crtc.c | 85 if (acrtc->otg_inst == -1) in amdgpu_dm_crtc_set_vupdate_irq()
88 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; in amdgpu_dm_crtc_set_vupdate_irq()
747 acrtc->otg_inst = -1; in amdgpu_dm_crtc_init()
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| H A D | amdgpu_dm_irq.c | 730 if (acrtc->otg_inst == -1) in dm_irq_state()
733 irq_source = dal_irq_type + acrtc->otg_inst; in dm_irq_state()
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| H A D | amdgpu_dm_hdcp.c | 567 display->controller = CONTROLLER_ID_D0 + config->otg_inst; in update_config()
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| H A D | amdgpu_dm.c | 348 int otg_inst) in get_crtc_by_otg_inst()
354 if (WARN_ON(otg_inst == -1)) in get_crtc_by_otg_inst()
360 if (amdgpu_crtc->otg_inst == otg_inst) in get_crtc_by_otg_inst()
3274 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; in dm_destroy_cached_state()
3295 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; in dm_suspend()
9898 acrtc->otg_inst = -1; in amdgpu_dm_update_cursor()
11051 acrtc->otg_inst = status->primary_otg_inst; in amdgpu_dm_atomic_commit_tail()
344 get_crtc_by_otg_inst(struct amdgpu_device * adev,int otg_inst) get_crtc_by_otg_inst() argument
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 530 unsigned char otg_inst; member
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_mode.h | 508 int otg_inst;
512 int otg_inst; global() member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_utils.c | 430 static_base_state->stream_v1.base.otg_inst = (uint8_t)context->stream_status[dc_stream_idx].primary_otg_inst; in dml21_build_fams2_stream_programming_v2()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 3375 uint32_t otg_inst = params->hubp_vtg_sel_params.otg_inst; in hwss_add_hubp_set_blank()
3378 hubp->funcs->hubp_vtg_sel(hubp, otg_inst); in hwss_add_hubp_set_blank()
4512 uint32_t otg_inst)
4517 seq_state->steps[*seq_state->num_steps].params.hubp_vtg_sel_params.otg_inst = otg_inst;
2977 uint32_t otg_inst = params->hubp_vtg_sel_params.otg_inst; hwss_hubp_vtg_sel() local
3832 hwss_add_hubp_vtg_sel(struct block_sequence_state * seq_state,struct hubp * hubp,uint32_t otg_inst) hwss_add_hubp_vtg_sel() argument
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| H A D | dc.c | 4484 update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; in commit_planes_for_stream()
4545 update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; in commit_planes_for_stream()
6692 uint8_t otg_inst = 0; in dc_capture_register_software_state()
6702 // get otg_inst in dc_capture_register_software_state()
6716 otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst; in dc_capture_register_software_state()
6735 cmd.smart_power_oled_enable.data.otg_inst = otg_inst; in dc_capture_register_software_state()
6135 uint8_t otg_inst = 0; dc_smart_power_oled_enable() local
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| H A D | dc_stream.c | 642 dwb->otg_inst = stream_status->primary_otg_inst; in dc_stream_fc_disable_writeback()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_utils.c | 261 pipe_ctx->pipe_dlg_param.otg_inst = (unsigned char)pipe_ctx->stream_res.tg->inst; in populate_pipe_ctx_dlg_params_from_dml()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 1239 dto_params.otg_inst = tg->inst; in dce110_disable_stream()
3435 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1; in dce110_enable_dp_link_output()
3438 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst); in dce110_enable_dp_link_output()
3351 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1; dce110_set_pipe() local
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