/linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/ |
H A D | dcn201_optc.c | 32 optc1->tg_regs->reg 35 optc1->base.ctx 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name 43 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc201_triplebuffer_lock() local 59 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc201_triplebuffer_unlock() local 75 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc201_validate_timing() local 99 if (timing->h_total > optc1->max_h_total || in optc201_validate_timing() 100 timing->v_total > optc1->max_v_total) in optc201_validate_timing() 103 if (h_blank < optc1->min_h_blank) in optc201_validate_timing() 106 if (timing->h_sync_width < optc1->min_h_sync_width || in optc201_validate_timing() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/ |
H A D | dcn20_optc.c | 31 optc1->tg_regs->reg 34 optc1->base.ctx 38 optc1->tg_shift->field_name, optc1->tg_mask->field_name 54 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc2_enable_crtc() local 89 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc2_set_gsl() local 110 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc2_set_gsl_source_select() local 137 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc2_set_dsc_config() local 155 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc2_get_dsc_status() local 164 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc2_set_odm_bypass() local 178 optc1->opp_count = 1; in optc2_set_odm_bypass() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn30/ |
H A D | dcn30_optc.c | 36 optc1->tg_regs->reg 39 optc1->base.ctx 43 optc1->tg_shift->field_name, optc1->tg_mask->field_name 47 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc3_triplebuffer_lock() local 62 TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true); in optc3_triplebuffer_lock() 67 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc3_lock_doublebuffer_enable() local 99 TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true); in optc3_lock_doublebuffer_enable() 104 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc3_lock_doublebuffer_disable() local 116 TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true); in optc3_lock_doublebuffer_disable() 121 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc3_lock() local [all …]
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H A D | dcn30_optc.h | 324 void dcn30_timing_generator_init(struct optc *optc1);
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/ |
H A D | dcn314_optc.c | 36 optc1->tg_regs->reg 39 optc1->base.ctx 43 optc1->tg_shift->field_name, optc1->tg_mask->field_name 53 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc314_set_odm_combine() local 102 optc1->opp_count = opp_cnt; in optc314_set_odm_combine() 107 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc314_enable_crtc() local 133 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc314_disable_crtc() local 154 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc314_phantom_crtc_post_enable() local 166 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc314_set_odm_bypass() local 183 optc1->opp_count = 1; in optc314_set_odm_bypass() [all …]
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H A D | dcn314_optc.h | 253 void dcn314_timing_generator_init(struct optc *optc1);
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn32/ |
H A D | dcn32_optc.c | 36 optc1->tg_regs->reg 39 optc1->base.ctx 43 optc1->tg_shift->field_name, optc1->tg_mask->field_name 48 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc32_set_odm_combine() local 97 optc1->opp_count = opp_cnt; in optc32_set_odm_combine() 102 struct optc *optc1 = DCN10TG_FROM_TG(tg); in optc32_get_odm_combine_segments() local 126 struct optc *optc1 = DCN10TG_FROM_TG(tg); in optc32_wait_odm_doublebuffer_pending_clear() local 133 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc32_set_h_timing_div_manual_mode() local 147 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc32_enable_crtc() local 173 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc32_disable_crtc() local [all …]
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H A D | dcn32_optc.h | 182 void dcn32_timing_generator_init(struct optc *optc1);
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn35/ |
H A D | dcn35_optc.c | 38 optc1->tg_regs->reg 41 optc1->base.ctx 45 optc1->tg_shift->field_name, optc1->tg_mask->field_name 61 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc35_set_odm_combine() local 109 optc1->opp_count = opp_cnt; in optc35_set_odm_combine() 114 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc35_enable_crtc() local 140 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc35_disable_crtc() local 172 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc35_phantom_crtc_post_enable() local 184 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc35_configure_crc() local 203 if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0) { in optc35_configure_crc() [all …]
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H A D | dcn35_optc.h | 72 void dcn35_timing_generator_init(struct optc *optc1); 74 void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable);
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn301/ |
H A D | dcn301_optc.c | 36 optc1->tg_regs->reg 39 optc1->base.ctx 43 optc1->tg_shift->field_name, optc1->tg_mask->field_name 56 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc301_set_drr() local 99 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc301_setup_manual_trigger() local 174 void dcn301_timing_generator_init(struct optc *optc1) in dcn301_timing_generator_init() argument 176 optc1->base.funcs = &dcn30_tg_funcs; in dcn301_timing_generator_init() 178 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn301_timing_generator_init() 179 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn301_timing_generator_init() 181 optc1->min_h_blank = 32; in dcn301_timing_generator_init() [all …]
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H A D | dcn301_optc.h | 32 void dcn301_timing_generator_init(struct optc *optc1);
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
H A D | dcn30_fpu.c | 37 optc1->tg_regs->reg 40 optc1->base.ctx 44 optc1->tg_shift->field_name, optc1->tg_mask->field_name 184 struct optc *optc1 = DCN10TG_FROM_TG(optc); in optc3_fpu_set_vrr_m_const() local
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn31/ |
H A D | dcn31_optc.h | 259 void dcn31_timing_generator_init(struct optc *optc1);
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