/linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/ |
H A D | dcn314_optc.c | 50 static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc314_set_odm_combine() argument 55 int h_active = segment_width * opp_cnt; in optc314_set_odm_combine() 64 if (opp_cnt == 4) { in optc314_set_odm_combine() 83 if (opp_cnt == 2) { in optc314_set_odm_combine() 88 } else if (opp_cnt == 4) { in optc314_set_odm_combine() 101 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc314_set_odm_combine() 102 optc1->opp_count = opp_cnt; in optc314_set_odm_combine()
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn30/ |
H A D | dcn30_optc.c | 218 void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc3_set_odm_combine() argument 232 ASSERT(opp_cnt == 2 || opp_cnt == 4); in optc3_set_odm_combine() 237 if (opp_cnt == 2) { in optc3_set_odm_combine() 242 } else if (opp_cnt == 4) { in optc3_set_odm_combine() 253 if (opp_cnt == 2) { in optc3_set_odm_combine() 258 } else if (opp_cnt == 4) { in optc3_set_odm_combine() 270 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc3_set_odm_combine() 271 optc1->opp_count = opp_cnt; in optc3_set_odm_combine()
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H A D | dcn30_optc.h | 354 void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn32/ |
H A D | dcn32_optc.c | 45 static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc32_set_odm_combine() argument 50 int h_active = segment_width * opp_cnt; in optc32_set_odm_combine() 59 if (opp_cnt == 4) { in optc32_set_odm_combine() 78 if (opp_cnt == 2) { in optc32_set_odm_combine() 83 } else if (opp_cnt == 4) { in optc32_set_odm_combine() 96 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc32_set_odm_combine() 97 optc1->opp_count = opp_cnt; in optc32_set_odm_combine()
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn35/ |
H A D | dcn35_optc.c | 58 static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc35_set_odm_combine() argument 63 int h_active = segment_width * opp_cnt; in optc35_set_odm_combine() 72 if (opp_cnt == 4) { in optc35_set_odm_combine() 91 if (opp_cnt == 2) { in optc35_set_odm_combine() 96 } else if (opp_cnt == 4) { in optc35_set_odm_combine() 108 REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc35_set_odm_combine() 109 optc1->opp_count = opp_cnt; in optc35_set_odm_combine()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
H A D | dcn32_hwseq.c | 1013 int opp_cnt = 1; in dcn32_update_dsc_on_stream() local 1029 opp_cnt++; in dcn32_update_dsc_on_stream() 1051 …am->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; in dcn32_update_dsc_on_stream() 1057 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in dcn32_update_dsc_on_stream() 1058 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in dcn32_update_dsc_on_stream() 1125 int opp_cnt = 0; in dcn32_update_odm() local 1130 opp_cnt = get_odm_config(pipe_ctx, opp_inst); in dcn32_update_odm() 1132 if (opp_cnt > 1) in dcn32_update_odm() 1135 opp_inst, opp_cnt, in dcn32_update_odm() 1269 int opp_cnt = 1; in dcn32_resync_fifo_dccg_dio() local [all …]
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
H A D | dcn35_hwseq.c | 325 int opp_cnt = 1; in update_dsc_on_stream() local 331 opp_cnt++; in update_dsc_on_stream() 352 …am->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; in update_dsc_on_stream() 358 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in update_dsc_on_stream() 359 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in update_dsc_on_stream() 370 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; in update_dsc_on_stream() 371 dsc_cfg.pic_width *= opp_cnt; in update_dsc_on_stream() 424 int opp_cnt = 0; in dcn35_update_odm() local 429 opp_cnt = get_odm_config(pipe_ctx, opp_inst); in dcn35_update_odm() 431 if (opp_cnt > 1) in dcn35_update_odm() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/ |
H A D | dcn20_optc.c | 181 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc2_set_odm_combine() argument 187 ASSERT(opp_cnt == 2); in optc2_set_odm_combine() 217 optc1->opp_count = opp_cnt; in optc2_set_odm_combine()
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H A D | dcn20_optc.h | 107 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
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/linux/drivers/gpu/drm/amd/display/dc/dcn314/ |
H A D | dcn314_dio_stream_encoder.c |
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/linux/drivers/gpu/drm/amd/display/dc/dio/dcn32/ |
H A D | dcn32_dio_stream_encoder.c | 259 if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1 in enc32_stream_encoder_dp_unblank()
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/linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/ |
H A D | dcn20_stream_encoder.c | 482 if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1) { in enc2_stream_encoder_dp_unblank()
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