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Searched refs:num_valid_sets (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c428 uint8_t i, num_valid_sets; in dcn31_build_watermark_ranges() local
430 num_valid_sets = 0; in dcn31_build_watermark_ranges()
437 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = in dcn31_build_watermark_ranges()
439 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = in dcn31_build_watermark_ranges()
442 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges()
443 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
445 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { in dcn31_build_watermark_ranges()
447 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn31_build_watermark_ranges()
450 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn31_build_watermark_ranges()
453 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn31_build_watermark_ranges()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c499 uint8_t i, num_valid_sets; in dcn314_build_watermark_ranges() local
501 num_valid_sets = 0; in dcn314_build_watermark_ranges()
508 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = in dcn314_build_watermark_ranges()
510 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = in dcn314_build_watermark_ranges()
513 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn314_build_watermark_ranges()
514 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges()
516 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { in dcn314_build_watermark_ranges()
518 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn314_build_watermark_ranges()
521 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn314_build_watermark_ranges()
524 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn314_build_watermark_ranges()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c885 uint8_t i, num_valid_sets; in dcn35_build_watermark_ranges() local
887 num_valid_sets = 0; in dcn35_build_watermark_ranges()
894 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = in dcn35_build_watermark_ranges()
896 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = in dcn35_build_watermark_ranges()
899 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn35_build_watermark_ranges()
900 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn35_build_watermark_ranges()
902 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { in dcn35_build_watermark_ranges()
904 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn35_build_watermark_ranges()
907 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn35_build_watermark_ranges()
910 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn35_build_watermark_ranges()
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