Searched refs:num_tx_sched_layers (Results 1 – 4 of 4) sorted by relevance
785 for (ln = 0; ln < pi->hw->num_tx_sched_layers; ln++) { in ice_sched_clear_rl_prof()884 hw->num_tx_sched_layers = 0; in ice_sched_cleanup_all()1135 return hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET; in ice_sched_get_qgrp_layer()1152 if (hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS) in ice_sched_get_vsi_layer()1153 return hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET; in ice_sched_get_vsi_layer()1154 else if (hw->num_tx_sched_layers == ICE_SCHED_5_LAYERS) in ice_sched_get_vsi_layer()1156 return hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET; in ice_sched_get_vsi_layer()1173 if (hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS) in ice_sched_get_agg_layer()1174 return hw->num_tx_sched_layers - ICE_AGG_LAYER_OFFSET; in ice_sched_get_agg_layer()1364 hw->num_tx_sched_layers = le16_to_cpu(buf->sched_props.logical_levels); in ice_sched_query_res_alloc()[all …]
2424 hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS) { in ice_cfg_tx_topo()2431 hw->num_tx_sched_layers == ICE_SCHED_5_LAYERS) { in ice_cfg_tx_topo()2446 hw->num_tx_sched_layers == ICE_SCHED_5_LAYERS) { in ice_cfg_tx_topo()
4459 u8 num_tx_sched_layers = hw->num_tx_sched_layers; in ice_init_tx_topology() local4467 if (hw->num_tx_sched_layers > num_tx_sched_layers) in ice_init_tx_topology()
5027 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); in ice_ena_vsi_txq()5256 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, in ice_ena_vsi_rdma_qset()