Searched refs:num_tiles (Results 1 – 7 of 7) sorted by relevance
101 u32 num_tiles; member
222 hwctx->num_tiles = args->num_tiles; in amdxdna_drm_create_hwctx_ioctl()
453 if (!hwctx->num_tiles) { in aie2_hwctx_col_list()464 hwctx->num_col = hwctx->num_tiles / ndev->metadata.core.row_count; in aie2_hwctx_col_list()
184 unsigned int num_tiles; member855 for (i = 0; i < ctx->num_tiles; i++) { in calc_tile_dimensions()1648 if (ctx->next_tile == ctx->num_tiles) { in do_tile_complete()1687 } else if (ctx->next_tile < ctx->num_tiles - 1) { in do_tile_complete()2114 ctx->num_tiles = d_image->num_cols * d_image->num_rows; in ipu_image_convert_prepare()2171 ctx->double_buffering = (ctx->num_tiles > 1 && in ipu_image_convert_prepare()2174 for (i = 1; i < ctx->num_tiles; i++) { in ipu_image_convert_prepare()2199 for (i = 1; i < ctx->num_tiles; i++) { in ipu_image_convert_prepare()
47 ``pisp_tile`` and the ``num_tiles`` fields of :c:type:`pisp_be_tiles_config`.
186 u32 num_tiles; member1405 tile_group->num_tiles = tile->tile_cols * tile->tile_rows; in vdec_av1_slice_setup_tile_group()1407 if (tile_group->num_tiles != tge_size || in vdec_av1_slice_setup_tile_group()1408 tile_group->num_tiles > V4L2_AV1_MAX_TILE_COUNT) { in vdec_av1_slice_setup_tile_group()1410 tge_size, tile_group->num_tiles); in vdec_av1_slice_setup_tile_group()1632 memcpy(lat_buf->tile_addr.va, instance->tile.va, 64 * instance->tile_group.num_tiles); in vdec_av1_slice_setup_lat_buffer()1674 for (tile_num = 0; tile_num < tile_group->num_tiles; tile_num++) { in vdec_av1_slice_setup_tile_buffer()
300 PISP_BE_CONTROL_NUM_TILES(job->config->num_tiles)); in pispbe_queue_job()697 if (config->num_tiles == 0 || in pisp_be_validate_config()698 config->num_tiles > PISP_BACK_END_NUM_TILES) { in pisp_be_validate_config()700 config->num_tiles); in pisp_be_validate_config()