| /linux/drivers/gpu/drm/amd/display/dc/dsc/ |
| H A D | dc_dsc.c | 103 timing->dsc_cfg.num_slices_h, in dc_bandwidth_in_kbps_from_timing()
163 const uint32_t num_slices_h,
172 const uint32_t num_slices_h,
492 config.num_slices_h, &dsc_common_caps, timing, link_encoding, range); in dc_dsc_compute_bandwidth_range()
771 const uint32_t num_slices_h, in compute_bpp_x16_from_target_bandwidth() argument
780 timing, num_slices_h, is_dp); in compute_bpp_x16_from_target_bandwidth()
800 const uint32_t num_slices_h, in decide_dsc_bandwidth_range() argument
837 range->max_target_bpp_x16, num_slices_h, dsc_caps->is_dp); in decide_dsc_bandwidth_range()
841 range->min_target_bpp_x16, num_slices_h, dsc_caps->is_dp); in decide_dsc_bandwidth_range()
859 const int num_slices_h, in decide_dsc_target_bpp_x16() argument
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dsc.h | 90 uint32_t bpp_x16, uint32_t num_slices_h, bool is_dp);
94 const int num_slices_h,
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| H A D | dc_hw_types.h | 861 uint32_t num_slices_h; /* Number of DSC slices - horizontal */ member
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
| H A D | dcn314_hwseq.c | 109 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in update_dsc_on_stream()
110 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in update_dsc_on_stream()
121 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; in update_dsc_on_stream()
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| H A D | dcn401_dsc.c | 222 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, in dsc_write_to_registers()
228 reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN, in dsc_write_to_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_dpms.c | 842 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in link_set_dsc_on_stream()
843 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in link_set_dsc_on_stream()
846 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); in link_set_dsc_on_stream()
853 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); in link_set_dsc_on_stream()
857 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; in link_set_dsc_on_stream()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| H A D | dcn35_hwseq.c | 355 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in update_dsc_on_stream()
356 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in update_dsc_on_stream()
367 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; in update_dsc_on_stream()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_stream.c | 115 stream->timing.dsc_cfg.num_slices_h = 0; in dc_stream_construct()
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| H A D | dc_resource.c | 4289 if (hactive % stream->timing.dsc_cfg.num_slices_h != 0) { in decide_hblank_borrow()
4290 ceil_slice_width = (hactive / stream->timing.dsc_cfg.num_slices_h) + 1; in decide_hblank_borrow()
4291 pipe_ctx->hblank_borrow = ceil_slice_width * stream->timing.dsc_cfg.num_slices_h - hactive; in decide_hblank_borrow()
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| H A D | dc.c | 3314 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 && in copy_stream_update_to_stream()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| H A D | dml21_translation_helper.c | 480 timing->dsc.overrides.num_slices = stream->timing.dsc_cfg.num_slices_h; in populate_dml21_timing_config_from_stream_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml2_translation_helper.c | 787 out->DSCSlices[location] = in->timing.dsc_cfg.num_slices_h; in populate_dml_output_cfg_from_stream_state()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1670 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in dcn20_validate_dsc()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 1438 stream->timing.dsc_cfg.num_slices_h; in build_audio_output()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm.c | 6873 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; in apply_dsc_policy_for_stream()
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