| /linux/drivers/gpu/drm/amd/display/dc/dsc/ |
| H A D | dc_dsc.c | 103 timing->dsc_cfg.num_slices_h, in dc_bandwidth_in_kbps_from_timing()
163 const uint32_t num_slices_h,
172 const uint32_t num_slices_h,
492 config.num_slices_h, &dsc_common_caps, timing, link_encoding, range); in dc_dsc_compute_bandwidth_range()
768 const uint32_t num_slices_h, in compute_bpp_x16_from_target_bandwidth() argument
777 timing, num_slices_h, is_dp); in compute_bpp_x16_from_target_bandwidth()
797 const uint32_t num_slices_h, in decide_dsc_bandwidth_range() argument
834 range->max_target_bpp_x16, num_slices_h, dsc_caps->is_dp); in decide_dsc_bandwidth_range()
838 range->min_target_bpp_x16, num_slices_h, dsc_caps->is_dp); in decide_dsc_bandwidth_range()
856 const int num_slices_h, in decide_dsc_target_bpp_x16() argument
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| H A D | dcn20_dsc.c | 181 DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h); in dsc_config_log()
377 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h); in dsc_prepare_config()
389 if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h || in dsc_prepare_config()
406 dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; in dsc_prepare_config()
415 dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0; in dsc_prepare_config()
418 …idth + dsc_cfg->dsc_padding + dsc_cfg->dc_dsc_cfg.num_slices_h - 1) / dsc_cfg->dc_dsc_cfg.num_slic… in dsc_prepare_config()
609 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, in dsc_write_to_registers()
615 reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN, in dsc_write_to_registers()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dsc.h | 91 uint32_t bpp_x16, uint32_t num_slices_h, bool is_dp);
95 const int num_slices_h,
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| H A D | dcn401_dsc.c | 228 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, in dsc_write_to_registers()
234 reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN, in dsc_write_to_registers()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_mst_types.c | 880 uint32_t num_slices_h; member
940 if (params[i].num_slices_h) in set_dsc_configs_from_fairness_vars()
941 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h; in set_dsc_configs_from_fairness_vars()
1242 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; in compute_mst_dsc_configs_for_link()
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| H A D | amdgpu_dm.c | 7316 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; in apply_dsc_policy_for_stream()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | dccg.h | 336 void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst, uint32_t num_slices_h);
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_dpms.c | 706 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in link_set_dsc_on_stream()
707 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in link_set_dsc_on_stream()
711 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); in link_set_dsc_on_stream()
718 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); in link_set_dsc_on_stream()
722 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; in link_set_dsc_on_stream()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 2277 int num_slices_h = params->dccg_set_dto_dscclk_params.num_slices_h; in hwss_dccg_set_dto_dscclk() local
2280 dccg->funcs->set_dto_dscclk(dccg, inst, num_slices_h); in hwss_dccg_set_dto_dscclk()
2367 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in hwss_dsc_calculate_and_set_config()
3173 struct dccg *dccg, int inst, int num_slices_h) in hwss_add_dccg_set_dto_dscclk() argument
3179 …_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.num_slices_h = num_slices_h; in hwss_add_dccg_set_dto_dscclk()
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| H A D | dc_stream.c | 122 stream->timing.dsc_cfg.num_slices_h = 0; in dc_stream_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 1563 int num_slices_h = stream->timing.dsc_cfg.num_slices_h / opp_cnt; in dcn401_add_dsc_sequence_for_odm_change() local
1568 otg_master->stream_res.dsc->inst, num_slices_h); in dcn401_add_dsc_sequence_for_odm_change()
1586 odm_pipe->stream_res.dsc->inst, num_slices_h); in dcn401_add_dsc_sequence_for_odm_change()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_translation_helper.c | 155 timing->dsc.overrides.num_slices = stream->timing.dsc_cfg.num_slices_h; in populate_dml21_timing_config_from_stream_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_translation_helper.c | 794 out->DSCSlices[location] = in->timing.dsc_cfg.num_slices_h; in populate_dml_output_cfg_from_stream_state()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1708 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in dcn20_validate_dsc()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 1374 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; in dcn20_populate_dml_pipes_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 1493 stream->timing.dsc_cfg.num_slices_h; in build_audio_output()
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