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Searched refs:num_levels (Results 1 – 25 of 49) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c122 clks->num_levels = 6; in get_default_clock_levels()
127 clks->num_levels = 6; in get_default_clock_levels()
132 clks->num_levels = 2; in get_default_clock_levels()
137 clks->num_levels = 0; in get_default_clock_levels()
224 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS; in pp_to_dc_clock_levels()
226 dc_clks->num_levels = pp_clks->count; in pp_to_dc_clock_levels()
231 for (i = 0; i < dc_clks->num_levels; i++) { in pp_to_dc_clock_levels()
244 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { in pp_to_dc_clock_levels_with_latency()
247 pp_clks->num_levels, in pp_to_dc_clock_levels_with_latency()
250 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS; in pp_to_dc_clock_levels_with_latency()
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/linux/drivers/firmware/arm_scmi/
H A Dvoltage.c99 u32 num_levels; in scmi_init_voltage_levels() local
101 num_levels = num_returned + num_remaining; in scmi_init_voltage_levels()
106 if (!num_levels || in scmi_init_voltage_levels()
110 num_levels, num_returned, num_remaining, v->id); in scmi_init_voltage_levels()
114 v->levels_uv = devm_kcalloc(dev, num_levels, sizeof(u32), GFP_KERNEL); in scmi_init_voltage_levels()
118 v->num_levels = num_levels; in scmi_init_voltage_levels()
153 if (!p->v->num_levels) { in iter_volt_levels_update_state()
158 st->max_resources = p->v->num_levels; in iter_volt_levels_update_state()
196 iter = ph->hops->iter_response_init(ph, &ops, v->num_levels, in scmi_voltage_levels_get()
205 v->num_levels = 0; in scmi_voltage_levels_get()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c81 …ck(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels) in dcn3_init_single_clock() argument
89 *num_levels = 2; in dcn3_init_single_clock()
93 *num_levels = ret & 0xFF; in dcn3_init_single_clock()
96 for (i = 0; i < *num_levels; i++) { in dcn3_init_single_clock()
112 unsigned int num_levels; in dcn3_init_clocks() local
135 &num_levels); in dcn3_init_clocks()
141 &num_levels); in dcn3_init_clocks()
146 &num_levels); in dcn3_init_clocks()
152 &num_levels); in dcn3_init_clocks()
157 &num_levels); in dcn3_init_clocks()
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/linux/drivers/video/backlight/
H A Dmp3309c.c205 int num_levels; in mp3309c_parse_fwnode() local
238 num_levels = ANALOG_I2C_NUM_LEVELS; in mp3309c_parse_fwnode()
251 num_levels = device_property_count_u32(dev, "brightness-levels"); in mp3309c_parse_fwnode()
252 if (num_levels < 2) in mp3309c_parse_fwnode()
256 num_levels = MP3309C_PWM_DEFAULT_NUM_LEVELS; in mp3309c_parse_fwnode()
261 pdata->levels = devm_kcalloc(dev, num_levels, sizeof(*pdata->levels), GFP_KERNEL); in mp3309c_parse_fwnode()
266 pdata->levels, num_levels); in mp3309c_parse_fwnode()
270 for (i = 0; i < num_levels; i++) in mp3309c_parse_fwnode()
274 pdata->max_brightness = num_levels - 1; in mp3309c_parse_fwnode()
H A Dpwm_bl.c222 unsigned int num_levels; in pwm_backlight_parse_dt() local
251 num_levels = length / sizeof(u32); in pwm_backlight_parse_dt()
254 if (num_levels > 0) { in pwm_backlight_parse_dt()
255 data->levels = devm_kcalloc(dev, num_levels, in pwm_backlight_parse_dt()
262 num_levels); in pwm_backlight_parse_dt()
287 unsigned int num_input_levels = num_levels; in pwm_backlight_parse_dt()
303 num_levels = (num_input_levels - 1) * num_steps + 1; in pwm_backlight_parse_dt()
305 num_levels); in pwm_backlight_parse_dt()
311 table = devm_kcalloc(dev, num_levels, sizeof(*table), in pwm_backlight_parse_dt()
344 data->max_brightness = num_levels - 1; in pwm_backlight_parse_dt()
/linux/fs/verity/
H A Denable.c75 const int num_levels = params->num_levels; in build_merkle_tree() local
94 for (level = -1; level < num_levels; level++) { in build_merkle_tree()
101 buffers[num_levels].data = root_hash; in build_merkle_tree()
102 buffers[num_levels].is_root_hash = true; in build_merkle_tree()
129 for (level = 0; level < num_levels; level++) { in build_merkle_tree()
155 for (level = 0; level < num_levels; level++) { in build_merkle_tree()
169 if (WARN_ON_ONCE(buffers[num_levels].filled != params->digest_size)) { in build_merkle_tree()
175 for (level = -1; level < num_levels; level++) in build_merkle_tree()
H A Dopen.c112 if (params->num_levels >= FS_VERITY_MAX_LEVELS) { in fsverity_init_merkle_tree_params()
119 blocks_in_level[params->num_levels++] = blocks; in fsverity_init_merkle_tree_params()
124 for (level = (int)params->num_levels - 1; level >= 0; level--) { in fsverity_init_merkle_tree_params()
H A Dfsverity_private.h51 unsigned int num_levels; /* number of levels in Merkle tree */ member
/linux/drivers/gpu/drm/radeon/
H A Dsumo_dpm.c345 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
352 for (i = 0; i < ps->num_levels - 1; i++) in sumo_program_bsp()
406 for (i = 0; i < ps->num_levels; i++) { in sumo_program_at()
407 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi; in sumo_program_at()
421 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) | in sumo_program_at()
422 CG_L(m_a * l[ps->num_levels - 1] / 100); in sumo_program_at()
668 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1]; in sumo_patch_boost_state()
741 dpm_ctrl4 |= (1 << (new_ps->num_levels - 1)); in sumo_program_wl()
757 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; in sumo_program_power_levels_0_to_n()
759 for (i = 0; i < new_ps->num_levels; i++) { in sumo_program_power_levels_0_to_n()
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H A Dtrinity_dpm.c798 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; in trinity_program_power_levels_0_to_n()
800 for (i = 0; i < new_ps->num_levels; i++) { in trinity_program_power_levels_0_to_n()
805 for (i = new_ps->num_levels; i < n_current_state_levels; i++) in trinity_program_power_levels_0_to_n()
921 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
922 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
935 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
936 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
1161 if (ps->num_levels <= 1) in trinity_dpm_force_performance_level()
1168 ret = trinity_dpm_n_levels_disabled(rdev, ps->num_levels - 1); in trinity_dpm_force_performance_level()
1172 for (i = 0; i < ps->num_levels; i++) { in trinity_dpm_force_performance_level()
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H A Dr100_track.h44 unsigned num_levels; member
H A Dkv_dpm.c1544 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1551 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1570 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1579 new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1984 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
1990 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2002 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2013 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2375 ps->num_levels = 1; in kv_patch_boot_state()
2420 ps->num_levels = index + 1; in kv_parse_pplib_clock_info()
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H A Dtrinity_dpm.h48 u32 num_levels; member
/linux/arch/arm64/kernel/
H A Dcacheinfo.c63 detect_cache_level(&this_cpu_ci->num_levels, &this_cpu_ci->num_leaves); in early_cache_level()
94 this_cpu_ci->num_levels = level; in init_cache_level()
106 for (idx = 0, level = 1; level <= this_cpu_ci->num_levels && in populate_cache_leaves()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c133 unsigned int *num_levels) in dcn32_init_single_clock() argument
142 *num_levels = 2; in dcn32_init_single_clock()
146 *num_levels = ret & 0xFF; in dcn32_init_single_clock()
149 for (i = 0; i < *num_levels; i++) { in dcn32_init_single_clock()
165 unsigned int num_levels; in dcn32_init_clocks() local
215 num_levels = num_entries_per_clk->num_dispclk_levels; in dcn32_init_clocks()
225 num_levels = num_entries_per_clk->num_dppclk_levels; in dcn32_init_clocks()
237 for (i = 0; i < num_levels; i++) in dcn32_init_clocks()
243 for (i = 0; i < num_levels; i++) in dcn32_init_clocks()
248 for (i = 0; i < num_levels; i++) in dcn32_init_clocks()
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/linux/drivers/gpu/drm/amd/include/
H A Ddm_pp_interface.h174 uint32_t num_levels; member
184 uint32_t num_levels; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
H A Ddce110_clk_mgr.c76 if (dc->sclk_lvls.num_levels == 0) in determine_sclk_from_bounding_box()
79 for (i = 0; i < dc->sclk_lvls.num_levels; i++) { in determine_sclk_from_bounding_box()
89 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; in determine_sclk_from_bounding_box()
/linux/arch/s390/kernel/
H A Dcache.c142 this_cpu_ci->num_levels = level; in init_cache_level()
156 for (idx = 0, level = 0; level < this_cpu_ci->num_levels && in populate_cache_leaves()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_clk_mgr.c160 unsigned int *num_levels) in dcn401_init_single_clock() argument
169 *num_levels = 2; in dcn401_init_single_clock()
173 *num_levels = ret & 0xFF; in dcn401_init_single_clock()
176 for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) { in dcn401_init_single_clock()
1379 unsigned int num_levels; in dcn401_get_memclk_states_from_smu() local
1408 num_levels = num_entries_per_clk->num_memclk_levels; in dcn401_get_memclk_states_from_smu()
1410 num_levels = num_entries_per_clk->num_fclk_levels; in dcn401_get_memclk_states_from_smu()
1413 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1; in dcn401_get_memclk_states_from_smu()
1415 if (clk_mgr->dpm_present && !num_levels) in dcn401_get_memclk_states_from_smu()
/linux/drivers/accel/amdxdna/
H A Daie2_solver.h95 u32 num_levels; /* available power levels */ member
H A Daie2_solver.c92 cu_clk_freq = xrs->cfg.clk_list.cu_clk_list[xrs->cfg.clk_list.num_levels - 1]; in sanity_check()
120 max_dpm_level = xrs->cfg.clk_list.num_levels - 1; in set_dpm_level()
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dkv_dpm.c1782 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1789 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1808 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1817 new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
2246 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2252 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2264 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2275 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2640 ps->num_levels = 1; in kv_patch_boot_state()
2685 ps->num_levels = index + 1; in kv_parse_pplib_clock_info()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Dfs_core.c52 .num_levels = num_levels_val,\
163 int num_levels; member
1362 if (ft_attr->level >= fs_prio->num_levels) { in __mlx5_create_flow_table()
2847 int num_levels, in _fs_create_prio() argument
2859 fs_prio->num_levels = num_levels; in _fs_create_prio()
2868 int num_levels) in fs_create_prio_chained() argument
2870 return _fs_create_prio(ns, prio, num_levels, FS_TYPE_PRIO_CHAINS); in fs_create_prio_chained()
2874 unsigned int prio, int num_levels) in fs_create_prio() argument
2876 return _fs_create_prio(ns, prio, num_levels, FS_TYPE_PRIO); in fs_create_prio()
2912 fs_prio = fs_create_prio(ns, prio++, prio_metadata->num_levels); in create_leaf_prios()
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/linux/include/linux/
H A Dcacheinfo.h78 unsigned int num_levels; member
/linux/lib/
H A Ddecompress_unlzma.c203 rc_bit_tree_decode(struct rc *rc, uint16_t *p, int num_levels, int *symbol) in rc_bit_tree_decode() argument
205 int i = num_levels; in rc_bit_tree_decode()
210 *symbol -= 1 << num_levels; in rc_bit_tree_decode()

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