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Searched refs:num_levels (Results 1 – 25 of 47) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c81 …ck(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels) in dcn3_init_single_clock() argument
89 *num_levels = 2; in dcn3_init_single_clock()
93 *num_levels = ret & 0xFF; in dcn3_init_single_clock()
96 for (i = 0; i < *num_levels; i++) { in dcn3_init_single_clock()
112 unsigned int num_levels; in dcn3_init_clocks() local
135 &num_levels); in dcn3_init_clocks()
141 &num_levels); in dcn3_init_clocks()
146 &num_levels); in dcn3_init_clocks()
152 &num_levels); in dcn3_init_clocks()
157 &num_levels); in dcn3_init_clocks()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dce112/
H A Ddce112_resource.c1095 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1097 clks.clocks_in_khz[clks.num_levels/8], 1000); in bw_calcs_data_update_from_pplib()
1099 clks.clocks_in_khz[clks.num_levels*2/8], 1000); in bw_calcs_data_update_from_pplib()
1101 clks.clocks_in_khz[clks.num_levels*3/8], 1000); in bw_calcs_data_update_from_pplib()
1103 clks.clocks_in_khz[clks.num_levels*4/8], 1000); in bw_calcs_data_update_from_pplib()
1105 clks.clocks_in_khz[clks.num_levels*5/8], 1000); in bw_calcs_data_update_from_pplib()
1107 clks.clocks_in_khz[clks.num_levels*6/8], 1000); in bw_calcs_data_update_from_pplib()
1120 (int64_t)clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier, in bw_calcs_data_update_from_pplib()
1123 (int64_t)clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier, in bw_calcs_data_update_from_pplib()
1131 eng_clks.data[eng_clks.num_levels in bw_calcs_data_update_from_pplib()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dce120/
H A Ddce120_resource.c939 &eng_clks) || eng_clks.num_levels == 0) { in bw_calcs_data_update_from_pplib()
941 eng_clks.num_levels = 8; in bw_calcs_data_update_from_pplib()
944 for (i = 0; i < eng_clks.num_levels; i++) { in bw_calcs_data_update_from_pplib()
952 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
954 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
956 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
958 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
960 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
962 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); in bw_calcs_data_update_from_pplib()
964 eng_clks.data[eng_clks.num_levels* in bw_calcs_data_update_from_pplib()
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/linux/drivers/video/backlight/
H A Dpwm_bl.c222 unsigned int num_levels; in pwm_backlight_parse_dt() local
251 num_levels = length / sizeof(u32); in pwm_backlight_parse_dt()
254 if (num_levels > 0) { in pwm_backlight_parse_dt()
255 data->levels = devm_kcalloc(dev, num_levels, in pwm_backlight_parse_dt()
262 num_levels); in pwm_backlight_parse_dt()
287 unsigned int num_input_levels = num_levels; in pwm_backlight_parse_dt()
303 num_levels = (num_input_levels - 1) * num_steps + 1; in pwm_backlight_parse_dt()
305 num_levels); in pwm_backlight_parse_dt()
311 table = devm_kcalloc(dev, num_levels, sizeof(*table), in pwm_backlight_parse_dt()
344 data->max_brightness = num_levels - 1; in pwm_backlight_parse_dt()
/linux/drivers/gpu/drm/radeon/
H A Dsumo_dpm.c345 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
352 for (i = 0; i < ps->num_levels - 1; i++) in sumo_program_bsp()
406 for (i = 0; i < ps->num_levels; i++) { in sumo_program_at()
407 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi; in sumo_program_at()
421 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) | in sumo_program_at()
422 CG_L(m_a * l[ps->num_levels - 1] / 100); in sumo_program_at()
668 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1]; in sumo_patch_boost_state()
741 dpm_ctrl4 |= (1 << (new_ps->num_levels - 1)); in sumo_program_wl()
757 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; in sumo_program_power_levels_0_to_n()
759 for (i = 0; i < new_ps->num_levels; i++) { in sumo_program_power_levels_0_to_n()
[all …]
H A Dtrinity_dpm.c798 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; in trinity_program_power_levels_0_to_n()
800 for (i = 0; i < new_ps->num_levels; i++) { in trinity_program_power_levels_0_to_n()
805 for (i = new_ps->num_levels; i < n_current_state_levels; i++) in trinity_program_power_levels_0_to_n()
921 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
922 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
935 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
936 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
1161 if (ps->num_levels <= 1) in trinity_dpm_force_performance_level()
1168 ret = trinity_dpm_n_levels_disabled(rdev, ps->num_levels - 1); in trinity_dpm_force_performance_level()
1172 for (i = 0; i < ps->num_levels; i++) { in trinity_dpm_force_performance_level()
[all …]
H A Dr100_track.h44 unsigned num_levels; member
H A Dkv_dpm.c1544 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1551 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1570 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1579 new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1984 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
1990 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2002 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2013 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2375 ps->num_levels = 1; in kv_patch_boot_state()
2420 ps->num_levels = index + 1; in kv_parse_pplib_clock_info()
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H A Dtrinity_dpm.h48 u32 num_levels; member
/linux/arch/arm64/kernel/
H A Dcacheinfo.c63 detect_cache_level(&this_cpu_ci->num_levels, &this_cpu_ci->num_leaves); in early_cache_level()
94 this_cpu_ci->num_levels = level; in init_cache_level()
106 for (idx = 0, level = 1; level <= this_cpu_ci->num_levels && in populate_cache_leaves()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c133 unsigned int *num_levels) in dcn32_init_single_clock() argument
142 *num_levels = 2; in dcn32_init_single_clock()
146 *num_levels = ret & 0xFF; in dcn32_init_single_clock()
149 for (i = 0; i < *num_levels; i++) { in dcn32_init_single_clock()
165 unsigned int num_levels; in dcn32_init_clocks() local
215 num_levels = num_entries_per_clk->num_dispclk_levels; in dcn32_init_clocks()
225 num_levels = num_entries_per_clk->num_dppclk_levels; in dcn32_init_clocks()
237 for (i = 0; i < num_levels; i++) in dcn32_init_clocks()
243 for (i = 0; i < num_levels; i++) in dcn32_init_clocks()
248 for (i = 0; i < num_levels; i++) in dcn32_init_clocks()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c1297 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1299 clks.clocks_in_khz[clks.num_levels/8], 1000); in bw_calcs_data_update_from_pplib()
1301 clks.clocks_in_khz[clks.num_levels*2/8], 1000); in bw_calcs_data_update_from_pplib()
1303 clks.clocks_in_khz[clks.num_levels*3/8], 1000); in bw_calcs_data_update_from_pplib()
1305 clks.clocks_in_khz[clks.num_levels*4/8], 1000); in bw_calcs_data_update_from_pplib()
1307 clks.clocks_in_khz[clks.num_levels*5/8], 1000); in bw_calcs_data_update_from_pplib()
1309 clks.clocks_in_khz[clks.num_levels*6/8], 1000); in bw_calcs_data_update_from_pplib()
1320 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1322 clks.clocks_in_khz[clks.num_levels>>1], 1000); in bw_calcs_data_update_from_pplib()
1335 clks.clocks_in_khz[clks.num_levels>> in bw_calcs_data_update_from_pplib()
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/linux/drivers/gpu/drm/i915/display/
H A Dskl_watermark.c331 for (level = display->wm.num_levels - 1; in skl_crtc_can_enable_sagv()
657 for (level = 0; level < display->wm.num_levels; level++) { in skl_cursor_allocation()
1465 for (level = display->wm.num_levels - 1; level >= 0; level--) { in skl_crtc_allocate_plane_ddb()
1549 for (level++; level < display->wm.num_levels; level++) { in skl_crtc_allocate_plane_ddb()
1946 for (level = 0; level < display->wm.num_levels; level++) { in skl_compute_wm_levels()
2244 for (level = display->wm.num_levels - 1; level >= 0; level--) { in skl_max_wm_level_for_vblank()
2286 crtc_state->wm_level_disabled = level < display->wm.num_levels - 1; in skl_wm_check_vblank()
2295 for (level++; level < display->wm.num_levels; level++) { in skl_wm_check_vblank()
2377 for (level = 0; level < display->wm.num_levels; level++) { in skl_plane_wm_equals()
2742 for (level = 0; level < display->wm.num_levels; level++) { in skl_plane_selected_wm_equals()
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/linux/arch/s390/kernel/
H A Dcache.c142 this_cpu_ci->num_levels = level; in init_cache_level()
156 for (idx = 0, level = 0; level < this_cpu_ci->num_levels && in populate_cache_leaves()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu10_hwmgr.c1217 clocks->num_levels = 0; in smu10_get_clock_by_type_with_latency()
1220 clocks->data[clocks->num_levels].clocks_in_khz = in smu10_get_clock_by_type_with_latency()
1222 clocks->data[clocks->num_levels].latency_in_us = latency_required ? in smu10_get_clock_by_type_with_latency()
1226 clocks->num_levels++; in smu10_get_clock_by_type_with_latency()
1271 clocks->num_levels = 0; in smu10_get_clock_by_type_with_voltage()
1274 clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10; in smu10_get_clock_by_type_with_voltage()
1275 clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol; in smu10_get_clock_by_type_with_voltage()
1276 clocks->num_levels++; in smu10_get_clock_by_type_with_voltage()
/linux/drivers/accel/amdxdna/
H A Daie2_solver.h95 u32 num_levels; /* available power levels */ member
H A Daie2_solver.c92 cu_clk_freq = xrs->cfg.clk_list.cu_clk_list[xrs->cfg.clk_list.num_levels - 1]; in sanity_check()
120 max_dpm_level = xrs->cfg.clk_list.num_levels - 1; in set_dpm_level()
/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c1321 ASSERT(fclks->num_levels); in dcn_bw_update_from_pplib_fclks()
1324 vmid0p72_idx = fclks->num_levels > 2 ? fclks->num_levels - 3 : 0; in dcn_bw_update_from_pplib_fclks()
1325 vnom0p8_idx = fclks->num_levels > 1 ? fclks->num_levels - 2 : 0; in dcn_bw_update_from_pplib_fclks()
1326 vmax0p9_idx = fclks->num_levels > 0 ? fclks->num_levels - 1 : 0; in dcn_bw_update_from_pplib_fclks()
1348 if (dcfclks->num_levels >= 3) { in dcn_bw_update_from_pplib_dcfclks()
1350 dc->dcn_soc->dcfclkv_mid0p72 = dcfclks->data[dcfclks->num_levels - 3].clocks_in_khz / 1000.0; in dcn_bw_update_from_pplib_dcfclks()
1351 dc->dcn_soc->dcfclkv_nom0p8 = dcfclks->data[dcfclks->num_levels - 2].clocks_in_khz / 1000.0; in dcn_bw_update_from_pplib_dcfclks()
1352 dc->dcn_soc->dcfclkv_max0p9 = dcfclks->data[dcfclks->num_levels - 1].clocks_in_khz / 1000.0; in dcn_bw_update_from_pplib_dcfclks()
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dkv_dpm.c1782 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1789 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1808 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1817 new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
2246 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2252 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2264 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2275 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2640 ps->num_levels = 1; in kv_patch_boot_state()
2685 ps->num_levels = index + 1; in kv_parse_pplib_clock_info()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_clk_mgr.c160 unsigned int *num_levels) in dcn401_init_single_clock() argument
169 *num_levels = 2; in dcn401_init_single_clock()
173 *num_levels = ret & 0xFF; in dcn401_init_single_clock()
176 for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) { in dcn401_init_single_clock()
1379 unsigned int num_levels; in dcn401_get_memclk_states_from_smu() local
1407 num_levels = max(num_entries_per_clk->num_memclk_levels, num_entries_per_clk->num_fclk_levels); in dcn401_get_memclk_states_from_smu()
1409 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1; in dcn401_get_memclk_states_from_smu()
1411 if (clk_mgr->dpm_present && !num_levels) in dcn401_get_memclk_states_from_smu()
/linux/include/linux/
H A Dcacheinfo.h78 unsigned int num_levels; member
/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Dfs_core.c52 .num_levels = num_levels_val,\
163 int num_levels; member
1363 if (ft_attr->level >= fs_prio->num_levels) { in __mlx5_create_flow_table()
2846 int num_levels, in _fs_create_prio() argument
2858 fs_prio->num_levels = num_levels; in _fs_create_prio()
2867 int num_levels) in fs_create_prio_chained() argument
2869 return _fs_create_prio(ns, prio, num_levels, FS_TYPE_PRIO_CHAINS); in fs_create_prio_chained()
2873 unsigned int prio, int num_levels) in fs_create_prio() argument
2875 return _fs_create_prio(ns, prio, num_levels, FS_TYPE_PRIO); in fs_create_prio()
2911 fs_prio = fs_create_prio(ns, prio++, prio_metadata->num_levels); in create_leaf_prios()
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/linux/fs/verity/
H A Dverify.c64 for (level = 0; level < params->num_levels; level++) { in fsverity_readahead()
218 for (level = 0; level < params->num_levels; level++) { in verify_data_block()
/linux/lib/
H A Ddecompress_unlzma.c203 rc_bit_tree_decode(struct rc *rc, uint16_t *p, int num_levels, int *symbol) in rc_bit_tree_decode() argument
205 int i = num_levels; in rc_bit_tree_decode()
210 *symbol -= 1 << num_levels; in rc_bit_tree_decode()
/linux/drivers/hwmon/
H A Daspeed-pwm-tacho.c820 u32 pwm_port, u8 num_levels) in aspeed_create_pwm_cooling() argument
830 cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL); in aspeed_create_pwm_cooling()
834 cdev->max_state = num_levels - 1; in aspeed_create_pwm_cooling()
837 num_levels); in aspeed_create_pwm_cooling()

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