/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | pppcielanes.c | 56 uint8_t encode_pcie_lane_width(uint32_t num_lanes) in encode_pcie_lane_width() argument 58 return pp_r600_encode_lanes[num_lanes]; in encode_pcie_lane_width() 61 uint8_t decode_pcie_lane_width(uint32_t num_lanes) in decode_pcie_lane_width() argument 63 return pp_r600_decoded_lanes[num_lanes]; in decode_pcie_lane_width()
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H A D | pppcielanes.h | 27 extern uint8_t encode_pcie_lane_width(uint32_t num_lanes); 28 extern uint8_t decode_pcie_lane_width(uint32_t num_lanes);
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/linux/drivers/media/i2c/adv748x/ |
H A D | adv748x-core.c | 367 tx->active_lanes = min(tx->num_lanes, 2U); in adv748x_link_setup() 380 tx->active_lanes = tx->num_lanes; in adv748x_link_setup() 613 unsigned int num_lanes; in adv748x_parse_csi2_lanes() local 623 num_lanes = vep.bus.mipi_csi2.num_data_lanes; in adv748x_parse_csi2_lanes() 626 if (num_lanes != 1 && num_lanes != 2 && num_lanes != 4) { in adv748x_parse_csi2_lanes() 628 num_lanes); in adv748x_parse_csi2_lanes() 632 state->txa.num_lanes = num_lanes; in adv748x_parse_csi2_lanes() 633 state->txa.active_lanes = num_lanes; in adv748x_parse_csi2_lanes() 634 adv_dbg(state, "TXA: using %u lanes\n", state->txa.num_lanes); in adv748x_parse_csi2_lanes() 638 if (num_lanes != 1) { in adv748x_parse_csi2_lanes() [all …]
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/linux/drivers/acpi/ |
H A D | mipi-disco-img.c | 492 int num_lanes = 0; in init_csi2_port() local 509 num_lanes = ret; in init_csi2_port() 511 if (num_lanes > ACPI_DEVICE_CSI2_DATA_LANES) { in init_csi2_port() 513 num_lanes); in init_csi2_port() 514 num_lanes = ACPI_DEVICE_CSI2_DATA_LANES; in init_csi2_port() 519 val, num_lanes); in init_csi2_port() 523 for (i = 0; i < num_lanes; i++) in init_csi2_port() 529 num_lanes); in init_csi2_port() 536 } else if (ret * BITS_PER_TYPE(u8) < num_lanes + 1) { in init_csi2_port() 538 ret * BITS_PER_TYPE(u8), num_lanes + 1); in init_csi2_port() [all …]
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/linux/drivers/gpu/drm/bridge/adv7511/ |
H A D | adv7533.c | 171 u32 num_lanes; in adv7533_parse_dt() local 173 of_property_read_u32(np, "adi,dsi-lanes", &num_lanes); in adv7533_parse_dt() 175 if (num_lanes < 1 || num_lanes > 4) in adv7533_parse_dt() 178 adv->num_dsi_lanes = num_lanes; in adv7533_parse_dt()
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/linux/drivers/phy/mediatek/ |
H A D | phy-mtk-pcie.c | 55 int num_lanes; member 122 for (i = 0; i < pcie_phy->data->num_lanes; i++) in mtk_pcie_phy_init() 184 pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes * in mtk_pcie_read_efuse() 189 for (i = 0; i < pcie_phy->data->num_lanes; i++) { in mtk_pcie_read_efuse() 245 .num_lanes = 2,
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H A D | phy-mtk-mipi-csi-0-5.c | 30 u32 num_lanes; member 184 if (priv->num_lanes != 4) { in mtk_mipi_cdphy_xlate() 231 ret = of_property_read_u32(dev->of_node, "num-lanes", &port->num_lanes); in mtk_mipi_cdphy_probe()
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/linux/drivers/gpu/drm/bridge/cadence/ |
H A D | cdns-mhdp8546-core.c | 633 values[1] = link->num_lanes; in cdns_mhdp_link_configure() 896 CDNS_DP_LANE_EN_LANES(mhdp->link.num_lanes)); in cdns_mhdp_link_training_init() 900 phy_cfg.dp.lanes = mhdp->link.num_lanes; in cdns_mhdp_link_training_init() 941 for (i = 0; i < mhdp->link.num_lanes; i++) { in cdns_mhdp_get_adjust_train() 1006 for (i = 0; i < mhdp->link.num_lanes; i++) { in cdns_mhdp_adjust_requested_eq() 1029 for (i = 0; i < mhdp->link.num_lanes; i++) { in cdns_mhdp_print_lt_status() 1039 mhdp->link.num_lanes, mhdp->link.rate / 100, in cdns_mhdp_print_lt_status() 1072 phy_cfg.dp.lanes = mhdp->link.num_lanes; in cdns_mhdp_link_training_channel_eq() 1084 cdns_mhdp_adjust_lt(mhdp, mhdp->link.num_lanes, in cdns_mhdp_link_training_channel_eq() 1087 r = drm_dp_clock_recovery_ok(link_status, mhdp->link.num_lanes); in cdns_mhdp_link_training_channel_eq() [all …]
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/linux/drivers/nvdimm/ |
H A D | region.c | 24 if (nd_region->num_lanes > num_online_cpus() in nd_region_probe() 25 && nd_region->num_lanes < num_possible_cpus() in nd_region_probe() 28 num_online_cpus(), nd_region->num_lanes, in nd_region_probe() 31 nd_region->num_lanes); in nd_region_probe()
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H A D | region_devs.c | 944 if (nd_region->num_lanes < nr_cpu_ids) { in nd_region_acquire_lane() 947 lane = cpu % nd_region->num_lanes; in nd_region_acquire_lane() 961 if (nd_region->num_lanes < nr_cpu_ids) { in nd_region_release_lane() 1068 nd_region->num_lanes = ndr_desc->num_lanes; in nd_region_create() 1108 ndr_desc->num_lanes = ND_MAX_LANES; in nvdimm_pmem_region_create() 1117 ndr_desc->num_lanes = ND_MAX_LANES; in nvdimm_volatile_region_create()
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/linux/drivers/gpu/drm/msm/dp/ |
H A D | dp_panel.c | 68 link_info->num_lanes = drm_dp_max_lane_count(dpcd); in msm_dp_panel_read_dpcd() 71 if (link_info->num_lanes > msm_dp_panel->max_dp_lanes) in msm_dp_panel_read_dpcd() 72 link_info->num_lanes = msm_dp_panel->max_dp_lanes; in msm_dp_panel_read_dpcd() 80 drm_dbg_dp(panel->drm_dev, "lane_count=%d\n", link_info->num_lanes); in msm_dp_panel_read_dpcd() 100 data_rate_khz = link_info->num_lanes * link_info->rate * 8; in msm_dp_panel_get_supported_bpp() 136 !is_lane_count_valid(msm_dp_panel->link_info.num_lanes) || in msm_dp_panel_read_sink_caps() 139 msm_dp_panel->link_info.num_lanes); in msm_dp_panel_read_sink_caps()
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H A D | dp_ctrl.c | 109 values[1] = link->num_lanes; in msm_dp_aux_link_configure() 158 config |= ((ctrl->link->link_params.num_lanes - 1) in msm_dp_ctrl_config_ctrl() 971 in.nlanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_calc_tu_parameters() 1071 lane_cnt = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_update_vx_px() 1148 ctrl->link->link_params.num_lanes)) { in msm_dp_ctrl_link_train_1() 1204 if (ctrl->link->link_params.num_lanes == 1) in msm_dp_ctrl_link_lane_down_shift() 1207 ctrl->link->link_params.num_lanes /= 2; in msm_dp_ctrl_link_lane_down_shift() 1260 ctrl->link->link_params.num_lanes)) { in msm_dp_ctrl_link_train_2() 1285 link_info.num_lanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_link_train() 1450 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_enable_mainlink_clocks() [all …]
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/linux/drivers/gpu/drm/bridge/ |
H A D | tc358767.c | 353 u8 num_lanes; member 566 if (tc->link.num_lanes == 2) in tc_srcctrl() 829 u8 revision, num_lanes; in tc_get_display_props() local 842 num_lanes = drm_dp_max_lane_count(tc->link.dpcd); in tc_get_display_props() 851 if (num_lanes > 2) { in tc_get_display_props() 853 num_lanes = 2; in tc_get_display_props() 856 tc->link.num_lanes = num_lanes; in tc_get_display_props() 877 tc->link.num_lanes, in tc_get_display_props() 1001 out_bw = tc->link.num_lanes * tc->link.rate; in tc_set_edp_video_mode() 1120 if (tc->link.num_lanes == 2) in tc_main_link_enable() [all …]
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/linux/drivers/pci/controller/dwc/ |
H A D | pcie-designware.c | 174 of_property_read_u32(np, "num-lanes", &pci->num_lanes); in dw_pcie_get_resources() 739 static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) in dw_pcie_link_set_max_link_width() argument 744 if (!num_lanes) in dw_pcie_link_set_max_link_width() 755 switch (num_lanes) { in dw_pcie_link_set_max_link_width() 773 dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes); in dw_pcie_link_set_max_link_width() 782 lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes); in dw_pcie_link_set_max_link_width() 1105 dw_pcie_link_set_max_link_width(pci, pci->num_lanes); in dw_pcie_setup()
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H A D | pcie-qcom-common.c | 73 reg |= FIELD_PREP(MARGINING_MAXLANES, pci->num_lanes) | in qcom_pcie_common_set_16gt_lane_margining()
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/linux/drivers/media/platform/ti/cal/ |
H A D | cal-camerarx.c | 51 u32 num_lanes = mipi_csi2->num_data_lanes; in cal_camerarx_get_ext_link_freq() local 68 freq = v4l2_get_link_freq(phy->source->ctrl_handler, bpp, 2 * num_lanes); in cal_camerarx_get_ext_link_freq() 110 u32 num_lanes = phy->cal->data->camerarx[phy->instance].num_lanes; in cal_camerarx_enable() local 114 regmap_field_write(phy->fields[F_LANEENABLE], (1 << num_lanes) - 1); in cal_camerarx_enable()
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H A D | cal.c | 172 .num_lanes = 4, 181 .num_lanes = 2, 204 .num_lanes = 5, 213 .num_lanes = 3, 229 .num_lanes = 5,
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/linux/drivers/staging/greybus/ |
H A D | gb-camera.h | 45 unsigned int num_lanes; member
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H A D | camera.c | 359 __u8 num_lanes; member 415 csi_cfg.num_lanes = GB_CAMERA_CSI_NUM_DATA_LANES; in gb_camera_setup_data_connection() 440 csi_params->num_lanes = csi_cfg.num_lanes; in gb_camera_setup_data_connection()
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/linux/drivers/gpu/drm/panel/ |
H A D | panel-novatek-nt35950.c | 82 u8 num_lanes; member 508 nt->dsi[i]->lanes = nt->desc->num_lanes; in nt35950_probe() 589 .num_lanes = 4,
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/linux/drivers/gpu/drm/amd/display/dc/hpo/dcn31/ |
H A D | dcn31_hpo_dp_link_encoder.c | 51 enum dc_lane_count num_lanes) in dcn31_hpo_dp_link_enc_enable() argument 73 NUM_LANES, num_lanes == LANE_COUNT_ONE ? 0 : num_lanes == LANE_COUNT_TWO ? 1 : 3); in dcn31_hpo_dp_link_enc_enable()
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/linux/drivers/staging/media/atomisp/include/linux/ |
H A D | atomisp_platform.h | 152 unsigned int num_lanes; member
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/linux/drivers/gpu/drm/msm/dsi/ |
H A D | dsi_host.c | 1702 int ret, i, len, num_lanes; in dsi_host_parse_lane_data() local 1713 num_lanes = drm_of_get_data_lanes_count(ep, 1, 4); in dsi_host_parse_lane_data() 1714 if (num_lanes < 0) { in dsi_host_parse_lane_data() 1716 return num_lanes; in dsi_host_parse_lane_data() 1719 msm_host->num_data_lanes = num_lanes; in dsi_host_parse_lane_data() 1722 num_lanes); in dsi_host_parse_lane_data() 1743 for (j = 0; j < num_lanes; j++) { in dsi_host_parse_lane_data() 1752 if (j == num_lanes) { in dsi_host_parse_lane_data()
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/linux/drivers/iio/adc/ |
H A D | ad9467.c | 145 unsigned int num_lanes; member 353 .num_lanes = 8, 369 .num_lanes = 6, 668 for (lane = 0; lane < st->info->num_lanes; lane++) { in ad9467_calibrate_apply()
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/linux/drivers/phy/tegra/ |
H A D | xusb-tegra124.c | 661 .num_lanes = ARRAY_SIZE(tegra124_usb2_lanes), 796 .num_lanes = ARRAY_SIZE(tegra124_ulpi_lanes), 1012 .num_lanes = ARRAY_SIZE(tegra124_hsic_lanes), 1200 .num_lanes = ARRAY_SIZE(tegra124_pcie_lanes), 1396 .num_lanes = ARRAY_SIZE(tegra124_sata_lanes),
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