| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | pppcielanes.c | 56 uint8_t encode_pcie_lane_width(uint32_t num_lanes) in encode_pcie_lane_width() argument
58 return pp_r600_encode_lanes[num_lanes]; in encode_pcie_lane_width()
61 uint8_t decode_pcie_lane_width(uint32_t num_lanes) in decode_pcie_lane_width() argument
63 return pp_r600_decoded_lanes[num_lanes]; in decode_pcie_lane_width()
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| H A D | pppcielanes.h | 27 extern uint8_t encode_pcie_lane_width(uint32_t num_lanes);
28 extern uint8_t decode_pcie_lane_width(uint32_t num_lanes);
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| /linux/drivers/media/i2c/adv748x/ |
| H A D | adv748x-core.c | 367 tx->active_lanes = min(tx->num_lanes, 2U); in adv748x_link_setup()
380 tx->active_lanes = tx->num_lanes; in adv748x_link_setup()
613 unsigned int num_lanes; in adv748x_parse_csi2_lanes() local
623 num_lanes = vep.bus.mipi_csi2.num_data_lanes; in adv748x_parse_csi2_lanes()
626 if (num_lanes != 1 && num_lanes != 2 && num_lanes != 4) { in adv748x_parse_csi2_lanes()
628 num_lanes); in adv748x_parse_csi2_lanes()
632 state->txa.num_lanes = num_lanes; in adv748x_parse_csi2_lanes()
633 state->txa.active_lanes = num_lanes; in adv748x_parse_csi2_lanes()
634 adv_dbg(state, "TXA: using %u lanes\n", state->txa.num_lanes); in adv748x_parse_csi2_lanes()
638 if (num_lanes != 1) { in adv748x_parse_csi2_lanes()
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| /linux/drivers/phy/ti/ |
| H A D | phy-j721e-wiz.c | 385 u32 num_lanes; member
418 u32 num_lanes = wiz->num_lanes; in wiz_p_mac_div_sel() local
422 for (i = 0; i < num_lanes; i++) { in wiz_p_mac_div_sel()
441 u32 num_lanes = wiz->num_lanes; in wiz_mode_select() local
446 for (i = 0; i < num_lanes; i++) { in wiz_mode_select()
470 u32 num_lanes = wiz->num_lanes; in wiz_init_raw_interface() local
474 for (i = 0; i < num_lanes; i++) { in wiz_init_raw_interface()
523 int num_lanes = wiz->num_lanes; in wiz_regfield_init() local
612 for (i = 0; i < num_lanes; i++) { in wiz_regfield_init()
1277 u32 num_lanes = wiz->num_lanes; in wiz_phy_reset_deassert() local
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| /linux/drivers/acpi/ |
| H A D | mipi-disco-img.c | 491 int num_lanes = 0; in init_csi2_port() local
508 num_lanes = ret; in init_csi2_port()
510 if (num_lanes > ACPI_DEVICE_CSI2_DATA_LANES) { in init_csi2_port()
512 num_lanes); in init_csi2_port()
513 num_lanes = ACPI_DEVICE_CSI2_DATA_LANES; in init_csi2_port()
518 val, num_lanes); in init_csi2_port()
522 for (i = 0; i < num_lanes; i++) in init_csi2_port()
528 num_lanes); in init_csi2_port()
535 } else if (ret * BITS_PER_TYPE(u8) < num_lanes + 1) { in init_csi2_port()
537 ret * BITS_PER_TYPE(u8), num_lanes + 1); in init_csi2_port()
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| /linux/drivers/phy/mediatek/ |
| H A D | phy-mtk-pcie.c | 55 int num_lanes; member
122 for (i = 0; i < pcie_phy->data->num_lanes; i++) in mtk_pcie_phy_init()
184 pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes * in mtk_pcie_read_efuse()
189 for (i = 0; i < pcie_phy->data->num_lanes; i++) { in mtk_pcie_read_efuse()
245 .num_lanes = 2,
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| H A D | phy-mtk-mipi-csi-0-5.c | 30 u32 num_lanes; member
184 if (priv->num_lanes != 4) { in mtk_mipi_cdphy_xlate()
231 ret = of_property_read_u32(dev->of_node, "num-lanes", &port->num_lanes); in mtk_mipi_cdphy_probe()
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| /linux/drivers/nvdimm/ |
| H A D | region.c | 24 if (nd_region->num_lanes > num_online_cpus() in nd_region_probe()
25 && nd_region->num_lanes < num_possible_cpus() in nd_region_probe()
28 num_online_cpus(), nd_region->num_lanes, in nd_region_probe()
31 nd_region->num_lanes); in nd_region_probe()
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| H A D | region_devs.c | 926 if (nd_region->num_lanes < nr_cpu_ids) { in nd_region_acquire_lane()
929 lane = cpu % nd_region->num_lanes; in nd_region_acquire_lane()
943 if (nd_region->num_lanes < nr_cpu_ids) { in nd_region_release_lane()
1049 nd_region->num_lanes = ndr_desc->num_lanes; in nd_region_create()
1089 ndr_desc->num_lanes = ND_MAX_LANES; in nvdimm_pmem_region_create()
1098 ndr_desc->num_lanes = ND_MAX_LANES; in nvdimm_volatile_region_create()
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| /linux/drivers/media/platform/cadence/ |
| H A D | cdns-csi2rx.c | 145 u8 num_lanes; member
287 fmt->bpp, 2 * csi2rx->num_lanes); in csi2rx_configure_ext_dphy()
292 csi2rx->num_lanes, cfg); in csi2rx_configure_ext_dphy()
326 reg = csi2rx->num_lanes << 8; in csi2rx_start()
327 for (i = 0; i < csi2rx->num_lanes; i++) { in csi2rx_start()
338 for (i = csi2rx->num_lanes; i < csi2rx->max_lanes; i++) { in csi2rx_start()
350 for (i = 0; i < csi2rx->num_lanes; i++) { in csi2rx_start()
794 csi2rx->num_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; in csi2rx_parse_dt()
795 if (csi2rx->num_lanes > csi2rx->max_lanes) { in csi2rx_parse_dt()
797 csi2rx->num_lanes); in csi2rx_parse_dt()
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| H A D | cdns-csi2tx.c | 116 unsigned int num_lanes; member
251 for (i = 0; i < csi2tx->num_lanes; i++) in csi2tx_dphy_init_finish()
273 for (i = 0; i < csi2tx->num_lanes; i++) in csi2tx_dphy_setup()
519 csi2tx->num_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; in csi2tx_check_lanes()
520 if (csi2tx->num_lanes > csi2tx->max_lanes) { in csi2tx_check_lanes()
527 for (i = 0; i < csi2tx->num_lanes; i++) { in csi2tx_check_lanes()
627 csi2tx->num_lanes, csi2tx->max_lanes, csi2tx->max_streams, in csi2tx_probe()
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| /linux/drivers/iio/adc/ |
| H A D | ad4080.c | 190 unsigned int num_lanes; member
589 ret = iio_backend_num_lanes_set(st->back, st->num_lanes); in ad4080_setup()
605 if (st->num_lanes > 1) { in ad4080_setup()
627 st->num_lanes = 1; in ad4080_properties_parse()
628 device_property_read_u32(dev, "adi,num-lanes", &st->num_lanes); in ad4080_properties_parse()
629 if (!st->num_lanes || st->num_lanes > 2) in ad4080_properties_parse()
632 st->num_lanes); in ad4080_properties_parse()
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| H A D | ad4851.c | 497 unsigned int opt_delay, num_lanes, delay, i, s; in ad4851_calibrate() local
509 num_lanes = indio_dev->num_channels; in ad4851_calibrate()
512 num_lanes = 1; in ad4851_calibrate()
565 for (i = 0; i < num_lanes; i++) { in ad4851_calibrate()
580 for (i = 0; i < num_lanes; i++) { in ad4851_calibrate()
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| H A D | adi-axi-adc.c | 459 unsigned int num_lanes) in axi_adc_num_lanes_set() argument
463 if (!num_lanes) in axi_adc_num_lanes_set()
468 FIELD_PREP(ADI_AXI_ADC_CTRL_NUM_LANES_MSK, num_lanes)); in axi_adc_num_lanes_set()
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| /linux/drivers/soundwire/ |
| H A D | mipi_disco.c | 202 dp0->num_lanes = nval; in sdw_slave_read_dp0()
204 dp0->num_lanes, sizeof(*dp0->lane_list), in sdw_slave_read_dp0()
211 dp0->lane_list, dp0->num_lanes); in sdw_slave_read_dp0()
347 dpn[i].num_lanes = nval; in sdw_slave_read_dpn()
349 dpn[i].num_lanes, sizeof(*dpn[i].lane_list), in sdw_slave_read_dpn()
356 dpn[i].lane_list, dpn[i].num_lanes); in sdw_slave_read_dpn()
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| /linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-usbdp.c | 881 int ret, i, num_lanes; in rk_udphy_parse_lane_mux_data() local
883 num_lanes = device_property_count_u32(udphy->dev, "rockchip,dp-lane-mux"); in rk_udphy_parse_lane_mux_data()
884 if (num_lanes < 0) { in rk_udphy_parse_lane_mux_data()
890 if (num_lanes != 2 && num_lanes != 4) in rk_udphy_parse_lane_mux_data()
895 udphy->dp_lane_sel, num_lanes); in rk_udphy_parse_lane_mux_data()
899 for (i = 0; i < num_lanes; i++) { in rk_udphy_parse_lane_mux_data()
908 for (j = i + 1; j < num_lanes; j++) { in rk_udphy_parse_lane_mux_data()
916 if (num_lanes == 2) { in rk_udphy_parse_lane_mux_data()
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| /linux/drivers/gpu/drm/bridge/ |
| H A D | tc358767.c | 361 u8 num_lanes; member
574 if (tc->link.num_lanes == 2) in tc_srcctrl()
837 u8 revision, num_lanes; in tc_get_display_props() local
850 num_lanes = drm_dp_max_lane_count(tc->link.dpcd); in tc_get_display_props()
859 if (num_lanes > 2) { in tc_get_display_props()
861 num_lanes = 2; in tc_get_display_props()
864 tc->link.num_lanes = num_lanes; in tc_get_display_props()
885 tc->link.num_lanes, in tc_get_display_props()
1009 out_bw = tc->link.num_lanes * tc->link.rate; in tc_set_edp_video_mode()
1128 if (tc->link.num_lanes == 2) in tc_main_link_enable()
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| /linux/drivers/gpu/drm/xlnx/ |
| H A D | zynqmp_dp.c | 408 u8 num_lanes; member
480 for (i = 0; i < dp->num_lanes; i++) { in zynqmp_dp_phy_init()
494 for (i = dp->num_lanes - 1; i >= 0; i--) { in zynqmp_dp_phy_init()
516 for (i = 0; i < dp->num_lanes; i++) { in zynqmp_dp_phy_exit()
523 for (i = 0; i < dp->num_lanes; i++) { in zynqmp_dp_phy_exit()
558 if (dp->num_lanes) in zynqmp_dp_phy_probe()
575 dp->num_lanes++; in zynqmp_dp_phy_probe()
594 ready = (1 << dp->num_lanes) - 1; in zynqmp_dp_phy_ready()
1712 dp->num_lanes); in __zynqmp_dp_bridge_detect()
2141 if (val > dp->num_lanes) in zynqmp_dp_lanes_set()
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| /linux/drivers/phy/cadence/ |
| H A D | phy-cadence-sierra.c | 349 u32 num_lanes; member
407 u32 num_lanes; member
578 for (i = 0; i < ins->num_lanes; i++) { in cdns_sierra_phy_init()
600 for (i = 0; i < ins->num_lanes; i++) { in cdns_sierra_phy_init()
949 if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes)) in cdns_sierra_get_optional()
1257 int i, j, node, mlane, num_lanes, ret; in cdns_sierra_phy_configure_multilink() local
1306 num_lanes = sp->phys[node].num_lanes; in cdns_sierra_phy_configure_multilink()
1323 for (i = 0; i < num_lanes; i++) { in cdns_sierra_phy_configure_multilink()
1345 for (i = 0; i < num_lanes; i++) { in cdns_sierra_phy_configure_multilink()
1472 sp->num_lanes += sp->phys[node].num_lanes; in cdns_sierra_phy_probe()
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| /linux/drivers/gpu/drm/msm/dp/ |
| H A D | dp_link.c | 762 link->msm_dp_link.link_params.num_lanes = link->request.test_lane_count; in msm_dp_link_process_link_training_request()
893 link->msm_dp_link.link_params.num_lanes); in msm_dp_link_process_phy_test_pattern_request()
900 link->msm_dp_link.link_params.num_lanes = link->request.test_lane_count; in msm_dp_link_process_phy_test_pattern_request()
960 link->msm_dp_link.link_params.num_lanes); in msm_dp_link_process_link_status_update()
963 link->msm_dp_link.link_params.num_lanes); in msm_dp_link_process_link_status_update()
1124 for (i = 0; i < msm_dp_link->link_params.num_lanes; i++) { in msm_dp_link_adjust_levels()
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| H A D | dp_link.h | 23 unsigned int num_lanes; member
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| /linux/include/linux/iio/ |
| H A D | backend.h | 191 int (*num_lanes_set)(struct iio_backend *back, unsigned int num_lanes);
239 int iio_backend_num_lanes_set(struct iio_backend *back, unsigned int num_lanes);
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| /linux/drivers/iio/ |
| H A D | industrialio-backend.c | 880 int iio_backend_num_lanes_set(struct iio_backend *back, unsigned int num_lanes) in iio_backend_num_lanes_set() argument
882 if (!num_lanes) in iio_backend_num_lanes_set()
885 return iio_backend_op_call(back, num_lanes_set, num_lanes); in iio_backend_num_lanes_set()
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| /linux/drivers/media/platform/ti/cal/ |
| H A D | cal.c | 172 .num_lanes = 4,
181 .num_lanes = 2,
204 .num_lanes = 5,
213 .num_lanes = 3,
229 .num_lanes = 5,
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| /linux/drivers/gpu/drm/msm/dsi/ |
| H A D | dsi_host.c | 1810 int ret, i, len, num_lanes; in dsi_host_parse_lane_data() local
1821 num_lanes = drm_of_get_data_lanes_count(ep, 1, 4); in dsi_host_parse_lane_data()
1822 if (num_lanes < 0) { in dsi_host_parse_lane_data()
1824 return num_lanes; in dsi_host_parse_lane_data()
1827 msm_host->num_data_lanes = num_lanes; in dsi_host_parse_lane_data()
1830 num_lanes); in dsi_host_parse_lane_data()
1851 for (j = 0; j < num_lanes; j++) { in dsi_host_parse_lane_data()
1860 if (j == num_lanes) { in dsi_host_parse_lane_data()
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