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Searched refs:num_lanes (Results 1 – 25 of 41) sorted by relevance

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/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dpppcielanes.c56 uint8_t encode_pcie_lane_width(uint32_t num_lanes) in encode_pcie_lane_width() argument
58 return pp_r600_encode_lanes[num_lanes]; in encode_pcie_lane_width()
61 uint8_t decode_pcie_lane_width(uint32_t num_lanes) in decode_pcie_lane_width() argument
63 return pp_r600_decoded_lanes[num_lanes]; in decode_pcie_lane_width()
H A Dpppcielanes.h27 extern uint8_t encode_pcie_lane_width(uint32_t num_lanes);
28 extern uint8_t decode_pcie_lane_width(uint32_t num_lanes);
/linux/drivers/media/i2c/adv748x/
H A Dadv748x-core.c367 tx->active_lanes = min(tx->num_lanes, 2U); in adv748x_link_setup()
380 tx->active_lanes = tx->num_lanes; in adv748x_link_setup()
613 unsigned int num_lanes; in adv748x_parse_csi2_lanes() local
623 num_lanes = vep.bus.mipi_csi2.num_data_lanes; in adv748x_parse_csi2_lanes()
626 if (num_lanes != 1 && num_lanes != 2 && num_lanes != 4) { in adv748x_parse_csi2_lanes()
628 num_lanes); in adv748x_parse_csi2_lanes()
632 state->txa.num_lanes = num_lanes; in adv748x_parse_csi2_lanes()
633 state->txa.active_lanes = num_lanes; in adv748x_parse_csi2_lanes()
634 adv_dbg(state, "TXA: using %u lanes\n", state->txa.num_lanes); in adv748x_parse_csi2_lanes()
638 if (num_lanes != 1) { in adv748x_parse_csi2_lanes()
[all …]
/linux/drivers/acpi/
H A Dmipi-disco-img.c491 int num_lanes = 0; in init_csi2_port() local
508 num_lanes = ret; in init_csi2_port()
510 if (num_lanes > ACPI_DEVICE_CSI2_DATA_LANES) { in init_csi2_port()
512 num_lanes); in init_csi2_port()
513 num_lanes = ACPI_DEVICE_CSI2_DATA_LANES; in init_csi2_port()
518 val, num_lanes); in init_csi2_port()
522 for (i = 0; i < num_lanes; i++) in init_csi2_port()
528 num_lanes); in init_csi2_port()
535 } else if (ret * BITS_PER_TYPE(u8) < num_lanes + 1) { in init_csi2_port()
537 ret * BITS_PER_TYPE(u8), num_lanes + 1); in init_csi2_port()
[all …]
/linux/drivers/phy/mediatek/
H A Dphy-mtk-pcie.c55 int num_lanes; member
122 for (i = 0; i < pcie_phy->data->num_lanes; i++) in mtk_pcie_phy_init()
184 pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes * in mtk_pcie_read_efuse()
189 for (i = 0; i < pcie_phy->data->num_lanes; i++) { in mtk_pcie_read_efuse()
245 .num_lanes = 2,
H A Dphy-mtk-mipi-csi-0-5.c30 u32 num_lanes; member
184 if (priv->num_lanes != 4) { in mtk_mipi_cdphy_xlate()
231 ret = of_property_read_u32(dev->of_node, "num-lanes", &port->num_lanes); in mtk_mipi_cdphy_probe()
/linux/drivers/nvdimm/
H A Dregion.c24 if (nd_region->num_lanes > num_online_cpus() in nd_region_probe()
25 && nd_region->num_lanes < num_possible_cpus() in nd_region_probe()
28 num_online_cpus(), nd_region->num_lanes, in nd_region_probe()
31 nd_region->num_lanes); in nd_region_probe()
H A Dregion_devs.c195 for (i = 0; i < nd_region->num_lanes; i++) in nd_region_release()
923 lane = raw_smp_processor_id() % nd_region->num_lanes; in nd_region_acquire_lane()
1002 nd_region->num_lanes = ndr_desc->num_lanes; in nd_region_create()
1003 if (!nd_region->num_lanes) in nd_region_create()
1005 nd_region->lane = kcalloc(nd_region->num_lanes, in nd_region_create()
1010 for (i = 0; i < nd_region->num_lanes; i++) in nd_region_create()
1067 ndr_desc->num_lanes = ND_MAX_LANES; in nvdimm_pmem_region_create()
1076 ndr_desc->num_lanes = ND_MAX_LANES; in nvdimm_volatile_region_create()
/linux/drivers/ufs/core/
H A Dufs-debugfs.c225 u32 num_lanes; in ufs_tx_eq_params_show() local
251 num_lanes = pwr_info->lane_tx; in ufs_tx_eq_params_show()
256 num_lanes = pwr_info->lane_rx; in ufs_tx_eq_params_show()
265 for (lane = 0; lane < num_lanes; lane++) in ufs_tx_eq_params_show()
305 u32 num_lanes; in ufs_tx_eqtr_record_show() local
340 num_lanes = pwr_info->lane_tx; in ufs_tx_eqtr_record_show()
346 num_lanes = pwr_info->lane_rx; in ufs_tx_eqtr_record_show()
361 for (lane = 0; lane < num_lanes; lane++) { in ufs_tx_eqtr_record_show()
/linux/drivers/iio/adc/
H A Dad7779.c781 static int ad7779_set_data_lines(struct iio_dev *indio_dev, u32 num_lanes) in ad7779_set_data_lines() argument
786 if (num_lanes != 1 && num_lanes != 2 && num_lanes != 4) in ad7779_set_data_lines()
789 ret = ad7779_set_sampling_frequency(st, num_lanes * AD7779_DEFAULT_SAMPLING_1LINE); in ad7779_set_data_lines()
793 ret = iio_backend_num_lanes_set(st->back, num_lanes); in ad7779_set_data_lines()
799 FIELD_PREP(AD7779_DOUT_FORMAT_MSK, 2 - ilog2(num_lanes))); in ad7779_set_data_lines()
868 u32 num_lanes; in ad7779_setup_backend() local
889 num_lanes = 4; in ad7779_setup_backend()
890 ret = device_property_read_u32(dev, "adi,num-lanes", &num_lanes); in ad7779_setup_backend()
894 return ad7779_set_data_lines(indio_dev, num_lanes); in ad7779_setup_backend()
H A Dad4080.c196 unsigned int num_lanes; member
712 ret = iio_backend_num_lanes_set(st->back[ch], st->num_lanes); in ad4080_setup_channel()
733 if (st->num_lanes > 1) { in ad4080_setup_channel()
769 st->num_lanes = 1; in ad4080_properties_parse()
770 device_property_read_u32(dev, "adi,num-lanes", &st->num_lanes); in ad4080_properties_parse()
771 if (!st->num_lanes || st->num_lanes > 2) in ad4080_properties_parse()
774 st->num_lanes); in ad4080_properties_parse()
H A Dad4851.c496 unsigned int opt_delay, num_lanes, delay, i, s; in ad4851_calibrate() local
508 num_lanes = indio_dev->num_channels; in ad4851_calibrate()
511 num_lanes = 1; in ad4851_calibrate()
564 for (i = 0; i < num_lanes; i++) { in ad4851_calibrate()
579 for (i = 0; i < num_lanes; i++) { in ad4851_calibrate()
H A Dadi-axi-adc.c487 unsigned int num_lanes) in axi_adc_num_lanes_set() argument
491 if (!num_lanes) in axi_adc_num_lanes_set()
496 FIELD_PREP(ADI_AXI_ADC_CTRL_NUM_LANES_MSK, num_lanes)); in axi_adc_num_lanes_set()
/linux/drivers/soundwire/
H A Dmipi_disco.c201 dp0->num_lanes = nval; in sdw_slave_read_dp0()
203 dp0->num_lanes, sizeof(*dp0->lane_list), in sdw_slave_read_dp0()
210 dp0->lane_list, dp0->num_lanes); in sdw_slave_read_dp0()
346 dpn[i].num_lanes = nval; in sdw_slave_read_dpn()
348 dpn[i].num_lanes, sizeof(*dpn[i].lane_list), in sdw_slave_read_dpn()
355 dpn[i].lane_list, dpn[i].num_lanes); in sdw_slave_read_dpn()
/linux/drivers/media/platform/cadence/
H A Dcdns-csi2tx.c116 unsigned int num_lanes; member
251 for (i = 0; i < csi2tx->num_lanes; i++) in csi2tx_dphy_init_finish()
273 for (i = 0; i < csi2tx->num_lanes; i++) in csi2tx_dphy_setup()
519 csi2tx->num_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; in csi2tx_check_lanes()
520 if (csi2tx->num_lanes > csi2tx->max_lanes) { in csi2tx_check_lanes()
527 for (i = 0; i < csi2tx->num_lanes; i++) { in csi2tx_check_lanes()
627 csi2tx->num_lanes, csi2tx->max_lanes, csi2tx->max_streams, in csi2tx_probe()
/linux/drivers/pci/controller/dwc/
H A Dpcie-eswin.c59 int num_lanes; member
149 if (!of_property_read_u32(node, "num-lanes", &port->num_lanes)) in eswin_pcie_parse_port()
150 pcie->pci.num_lanes = port->num_lanes; in eswin_pcie_parse_port()
H A Dpcie-nxp-s32g.c247 int num_lanes; in s32g_pcie_parse_port() local
267 if (!of_property_read_u32(node, "num-lanes", &num_lanes)) in s32g_pcie_parse_port()
268 s32g_pp->pci.num_lanes = num_lanes; in s32g_pcie_parse_port()
H A Dpcie-qcom-common.c71 FIELD_MODIFY(MARGINING_MAXLANES, &reg, pci->num_lanes); in qcom_pcie_common_set_16gt_lane_margining()
/linux/drivers/pci/controller/
H A Dpcie-mediatek-gen3.c220 u8 num_lanes; member
505 if (pcie->num_lanes) { in mtk_pcie_startup_port()
509 if (pcie->num_lanes > 1) in mtk_pcie_startup_port()
511 GENMASK(fls(pcie->num_lanes >> 2), 0)); in mtk_pcie_startup_port()
934 u32 num_lanes; in mtk_pcie_parse_port() local
965 ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes); in mtk_pcie_parse_port()
967 if (num_lanes == 0 || num_lanes > 16 || in mtk_pcie_parse_port()
968 (num_lanes != 1 && num_lanes % 2)) in mtk_pcie_parse_port()
971 pcie->num_lanes = num_lanes; in mtk_pcie_parse_port()
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-usbdp.c880 int ret, i, num_lanes; in rk_udphy_parse_lane_mux_data() local
882 num_lanes = device_property_count_u32(udphy->dev, "rockchip,dp-lane-mux"); in rk_udphy_parse_lane_mux_data()
883 if (num_lanes < 0) { in rk_udphy_parse_lane_mux_data()
889 if (num_lanes != 2 && num_lanes != 4) in rk_udphy_parse_lane_mux_data()
894 udphy->dp_lane_sel, num_lanes); in rk_udphy_parse_lane_mux_data()
898 for (i = 0; i < num_lanes; i++) { in rk_udphy_parse_lane_mux_data()
907 for (j = i + 1; j < num_lanes; j++) { in rk_udphy_parse_lane_mux_data()
915 if (num_lanes == 2) { in rk_udphy_parse_lane_mux_data()
/linux/drivers/phy/cadence/
H A Dphy-cadence-sierra.c349 u32 num_lanes; member
407 u32 num_lanes; member
578 for (i = 0; i < ins->num_lanes; i++) { in cdns_sierra_phy_init()
600 for (i = 0; i < ins->num_lanes; i++) { in cdns_sierra_phy_init()
949 if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes)) in cdns_sierra_get_optional()
1257 int i, j, node, mlane, num_lanes, ret; in cdns_sierra_phy_configure_multilink() local
1306 num_lanes = sp->phys[node].num_lanes; in cdns_sierra_phy_configure_multilink()
1323 for (i = 0; i < num_lanes; i++) { in cdns_sierra_phy_configure_multilink()
1345 for (i = 0; i < num_lanes; i++) { in cdns_sierra_phy_configure_multilink()
1472 sp->num_lanes += sp->phys[node].num_lanes; in cdns_sierra_phy_probe()
[all …]
/linux/drivers/phy/freescale/
H A Dphy-fsl-lynx-10g.c516 .num_lanes = 4,
592 .num_lanes = 4,
636 .num_lanes = 4,
722 .num_lanes = 4,
807 .num_lanes = 8,
845 .num_lanes = 8,
/linux/drivers/gpu/drm/msm/dp/
H A Ddp_link.c762 link->msm_dp_link.link_params.num_lanes = link->request.test_lane_count; in msm_dp_link_process_link_training_request()
893 link->msm_dp_link.link_params.num_lanes); in msm_dp_link_process_phy_test_pattern_request()
900 link->msm_dp_link.link_params.num_lanes = link->request.test_lane_count; in msm_dp_link_process_phy_test_pattern_request()
960 link->msm_dp_link.link_params.num_lanes); in msm_dp_link_process_link_status_update()
963 link->msm_dp_link.link_params.num_lanes); in msm_dp_link_process_link_status_update()
1124 for (i = 0; i < msm_dp_link->link_params.num_lanes; i++) { in msm_dp_link_adjust_levels()
H A Ddp_link.h23 unsigned int num_lanes; member
/linux/drivers/media/platform/ti/cal/
H A Dcal.c172 .num_lanes = 4,
181 .num_lanes = 2,
204 .num_lanes = 5,
213 .num_lanes = 3,
229 .num_lanes = 5,

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