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Searched refs:num_entries_per_clk (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_clk_mgr.c82 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_socclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
86 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_memclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
90 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
94 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
98 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
105 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
109 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
219 struct clk_limit_num_entries *num_entries_per_clk; in dcn401_init_clocks() local
225 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; in dcn401_init_clocks()
246 &num_entries_per_clk->num_dcfclk_levels); in dcn401_init_clocks()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c166 struct clk_limit_num_entries *num_entries_per_clk; in dcn32_init_clocks() local
172 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; in dcn32_init_clocks()
193 &num_entries_per_clk->num_dcfclk_levels); in dcn32_init_clocks()
199 &num_entries_per_clk->num_socclk_levels); in dcn32_init_clocks()
206 &num_entries_per_clk->num_dtbclk_levels); in dcn32_init_clocks()
214 &num_entries_per_clk->num_dispclk_levels); in dcn32_init_clocks()
215 num_levels = num_entries_per_clk->num_dispclk_levels; in dcn32_init_clocks()
224 &num_entries_per_clk->num_dppclk_levels); in dcn32_init_clocks()
225 num_levels = num_entries_per_clk->num_dppclk_levels; in dcn32_init_clocks()
231 if (num_entries_per_clk->num_dcfclk_levels && in dcn32_init_clocks()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c403 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = num_uclk_dpms; in build_synthetic_soc_states()
404 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = num_fclk_dpms; in build_synthetic_soc_states()
869 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn321_update_bw_bounding_box_fpu()
870 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; in dcn321_update_bw_bounding_box_fpu()
872 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = in dcn321_update_bw_bounding_box_fpu()
873 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels; in dcn321_update_bw_bounding_box_fpu()
875 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels = in dcn321_update_bw_bounding_box_fpu()
876 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; in dcn321_update_bw_bounding_box_fpu()
878 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels = in dcn321_update_bw_bounding_box_fpu()
879 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; in dcn321_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/
H A Ddml21_translation_helper.c100 if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { in override_dml_init_with_values_from_smu()
101 dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; in override_dml_init_with_values_from_smu()
123 if (dc_clk_table->num_entries_per_clk.num_fclk_levels) { in override_dml_init_with_values_from_smu()
124 dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_fclk_levels; in override_dml_init_with_values_from_smu()
146 if (dc_clk_table->num_entries_per_clk.num_memclk_levels) { in override_dml_init_with_values_from_smu()
147 dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels; in override_dml_init_with_values_from_smu()
169 if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) { in override_dml_init_with_values_from_smu()
170 dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels; in override_dml_init_with_values_from_smu()
192 if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) { in override_dml_init_with_values_from_smu()
193 dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels; in override_dml_init_with_values_from_smu()
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h144 struct clk_limit_num_entries num_entries_per_clk; member
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_translation_helper.c522 …for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels; i++)… in dml2_init_soc_states()
530 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels; i++) { in dml2_init_soc_states()
535 …for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels; i++)… in dml2_init_soc_states()
540 …for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels; i++)… in dml2_init_soc_states()
545 …for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels; i++)… in dml2_init_soc_states()
551 …for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels; i++… in dml2_init_soc_states()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c1757 …for (int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; … in dcn401_get_power_profile()