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Searched refs:num_clk_values (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/
H A Ddml2_mcg_dcn4.c50 if (soc_bb->clk_table.dcfclk.num_clk_values == 2) { in build_min_clk_table_fine_grained()
54 if (soc_bb->clk_table.fclk.num_clk_values == 2) { in build_min_clk_table_fine_grained()
62 for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) { in build_min_clk_table_fine_grained()
67 min_table->dram_bw_table.num_entries = soc_bb->clk_table.uclk.num_clk_values; in build_min_clk_table_fine_grained()
76 …ies[i].min_fclk_khz, soc_bb->clk_table.fclk.clk_values_khz, soc_bb->clk_table.fclk.num_clk_values); in build_min_clk_table_fine_grained()
101 ….min_dcfclk_khz, soc_bb->clk_table.dcfclk.clk_values_khz, soc_bb->clk_table.dcfclk.num_clk_values); in build_min_clk_table_fine_grained()
137 for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) { in build_min_clk_table_coarse_grained()
142 min_table->dram_bw_table.num_entries = soc_bb->clk_table.uclk.num_clk_values; in build_min_clk_table_coarse_grained()
155 if (soc_bb->clk_table.dcfclk.num_clk_values < 2 || soc_bb->clk_table.fclk.num_clk_values < 2) in build_min_clock_table()
158 if (soc_bb->clk_table.uclk.num_clk_values > DML_MCG_MAX_CLK_TABLE_SIZE) in build_min_clock_table()
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/
H A Ddcn4_soc_bb.h88 .num_clk_values = 1,
92 .num_clk_values = 2,
96 .num_clk_values = 2,
100 .num_clk_values = 2,
104 .num_clk_values = 2,
108 .num_clk_values = 2,
112 .num_clk_values = 2,
116 .num_clk_values = 2,
120 .num_clk_values = 2,
124 .num_clk_values = 2,
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H A Ddcn3_soc_bb.h138 .num_clk_values = 4,
142 .num_clk_values = 2,
146 .num_clk_values = 2,
150 .num_clk_values = 2,
154 .num_clk_values = 2,
158 .num_clk_values = 2,
162 .num_clk_values = 2,
166 .num_clk_values = 2,
170 .num_clk_values = 2,
174 .num_clk_values = 2,
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/
H A Ddml21_translation_helper.c108 dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; in dml21_apply_soc_bb_overrides()
110 if (i < dml_clk_table->dcfclk.num_clk_values) { in dml21_apply_soc_bb_overrides()
115 dml_clk_table->dcfclk.num_clk_values = i + 1; in dml21_apply_soc_bb_overrides()
118 dml_clk_table->dcfclk.num_clk_values = i; in dml21_apply_soc_bb_overrides()
131 dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_fclk_levels; in dml21_apply_soc_bb_overrides()
133 if (i < dml_clk_table->fclk.num_clk_values) { in dml21_apply_soc_bb_overrides()
138 dml_clk_table->fclk.num_clk_values = i + 1; in dml21_apply_soc_bb_overrides()
141 dml_clk_table->fclk.num_clk_values = i; in dml21_apply_soc_bb_overrides()
154 dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels; in dml21_apply_soc_bb_overrides()
156 if (i < dml_clk_table->uclk.num_clk_values) { in dml21_apply_soc_bb_overrides()
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H A Ddml21_wrapper.c171 if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) { in dml21_calculate_rq_and_dlg_params()
173 …_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values] * 1000; in dml21_calculate_rq_and_dlg_params()
178 if (in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values > 1) { in dml21_calculate_rq_and_dlg_params()
180 …lk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values] * 1000; in dml21_calculate_rq_and_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
H A Ddml2_dpmm_dcn4.c231 if (clock_table->num_clk_values > 2) { in round_up_and_copy_to_next_dpm()
232 while (index < clock_table->num_clk_values && clock_table->clk_values_khz[index] < min_value) in round_up_and_copy_to_next_dpm()
235 if (index < clock_table->num_clk_values) { in round_up_and_copy_to_next_dpm()
239 } else if (clock_table->clk_values_khz[clock_table->num_clk_values - 1] >= min_value) { in round_up_and_copy_to_next_dpm()
284 for (index = 0; index < state_table->uclk.num_clk_values; index++) { in map_soc_min_clocks_to_dpm_coarse_grained()
298 for (index = 0; index < state_table->uclk.num_clk_values; index++) { in map_soc_min_clocks_to_dpm_coarse_grained()
328 if (state_table->dcfclk.num_clk_values == 2) { in map_min_clocks_to_dpm()
332 if (state_table->fclk.num_clk_values == 2) { in map_min_clocks_to_dpm()
336 if (state_table->fclk.num_clk_values == state_table->dcfclk.num_clk_values && in map_min_clocks_to_dpm()
337 state_table->fclk.num_clk_values == state_table->uclk.num_clk_values) { in map_min_clocks_to_dpm()
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
H A Ddml_top_soc_parameter_types.h106 unsigned char num_clk_values; member
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
H A Ddml2_core_utils.c385 for (i = 0; i < clk_table->uclk.num_clk_values; i++) { in dml2_core_utils_get_active_min_uclk_dpm_index()
H A Ddml2_core_dcn4.c525 for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) { in lookup_uclk_dpm_index_by_freq()
H A Ddml2_core_shared.c9016 for (i = 0; i < clk_table->uclk.num_clk_values; i++) { in get_active_min_uclk_dpm_index()
11388 …e_lib->soc.clk_table.uclk.clk_values_khz[mode_lib->soc.clk_table.uclk.num_clk_values - 1] / 1000.0; in dml2_core_shared_mode_programming()
H A Ddml2_core_dcn4_calcs.c6845 for (i = 0; i < clk_table->uclk.num_clk_values; i++) { in get_active_min_uclk_dpm_index()
11566 …e_lib->soc.clk_table.uclk.clk_values_khz[mode_lib->soc.clk_table.uclk.num_clk_values - 1] / 1000.0; in dml_core_mode_programming()