Searched refs:num_active_pipes (Results 1 – 8 of 8) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_utils.c | 389 unsigned int num_active_pipes = 0; in dml2_core_util_get_num_active_pipes() local
392 …num_active_pipes = num_active_pipes + (unsigned int)cfg_support_info->plane_support_info[k].dpps_u… in dml2_core_util_get_num_active_pipes()
396 DML_LOG_VERBOSE("DML::%s: num_active_pipes = %d\n", __func__, num_active_pipes); in dml2_core_util_get_num_active_pipes()
398 return num_active_pipes; in dml2_core_util_get_num_active_pipes()
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| H A D | dml2_core_shared_types.h | 920 unsigned int num_active_pipes; member
1680 unsigned int num_active_pipes; member
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| H A D | dml2_core_dcn6_calcs_dchub.c | 743 l->num_active_pipes = mode_lib->mp.num_active_pipes; in dcn6_rq_dlg_get_dlg_reg()
753 for (unsigned int i = 0; i < l->num_active_pipes; i++) { in dcn6_rq_dlg_get_dlg_reg()
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| H A D | dml2_core_dcn5_funcs_mode_programming.c | 44 …mode_lib->mp.num_active_pipes = dml2_core_util_get_num_active_pipes(display_cfg->num_planes, cfg_s… in dcn5_mode_programming()
111 DML_LOG_VERBOSE("DML::%s: num_active_pipes = %u\n", __func__, mode_lib->mp.num_active_pipes); in dcn5_mode_programming()
122 for (k = 0; k < mode_lib->mp.num_active_pipes; ++k) { in dcn5_mode_programming()
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| H A D | dml2_core_dcn5_calcs_dchub.c | 5577 l->num_active_pipes = mode_lib->mp.num_active_pipes; in dcn5_rq_dlg_get_dlg_reg()
5587 for (unsigned int i = 0; i < l->num_active_pipes; i++) { in dcn5_rq_dlg_get_dlg_reg()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml_display_rq_dlg_calc.c | 293 dml_uint_t num_active_pipes = dml_get_num_active_pipes(&mode_lib->ms.cache_display_cfg); in dml_rq_dlg_get_dlg_reg() local
298 for (dml_uint_t i = 0; i < num_active_pipes; i++) { in dml_rq_dlg_get_dlg_reg()
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| H A D | display_mode_core_structs.h | 1137 dml_uint_t num_active_pipes; member
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_cdclk.c | 2731 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; in intel_cdclk_pcode_pre_notify() local
2763 num_active_pipes = dg2_power_well_count(display, new_cdclk_state); in intel_cdclk_pcode_pre_notify()
2765 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, in intel_cdclk_pcode_pre_notify()
2776 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; in intel_cdclk_pcode_post_notify() local
2800 num_active_pipes = dg2_power_well_count(display, new_cdclk_state); in intel_cdclk_pcode_post_notify()
2802 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, in intel_cdclk_pcode_post_notify()
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