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Searched refs:nbio (Results 1 – 25 of 53) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_nbio.c30 if (!adev->nbio.ras) in amdgpu_nbio_ras_sw_init()
33 ras = adev->nbio.ras; in amdgpu_nbio_ras_sw_init()
43 adev->nbio.ras_if = &ras->ras_block.ras_comm; in amdgpu_nbio_ras_sw_init()
50 if (adev->nbio.funcs && adev->nbio.funcs->get_pcie_replay_count) in amdgpu_nbio_get_pcie_replay_count()
51 return adev->nbio.funcs->get_pcie_replay_count(adev); in amdgpu_nbio_get_pcie_replay_count()
64 r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0); in amdgpu_nbio_ras_late_init()
67 r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); in amdgpu_nbio_ras_late_init()
H A Dsoc24.c94 return adev->nbio.funcs->get_memsize(adev); in soc24_get_config_memsize()
249 (adev->nbio.funcs->program_aspm)) in soc24_program_aspm()
250 adev->nbio.funcs->program_aspm(adev); in soc24_program_aspm()
370 adev->nbio.funcs->set_reg_remap(adev); in soc24_common_early_init()
450 if (adev->nbio.ras && in soc24_common_late_init()
451 adev->nbio.ras_err_event_athub_irq.funcs) in soc24_common_late_init()
457 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); in soc24_common_late_init()
463 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); in soc24_common_late_init()
485 adev->nbio.funcs->init_registers(adev); in soc24_common_hw_init()
490 if (adev->nbio.funcs->remap_hdp_registers) in soc24_common_hw_init()
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H A Dsoc15.c344 return adev->nbio.funcs->get_memsize(adev); in soc15_get_config_memsize()
515 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); in soc15_asic_baco_reset()
523 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); in soc15_asic_baco_reset()
702 if (adev->nbio.funcs->program_aspm) in soc15_program_aspm()
703 adev->nbio.funcs->program_aspm(adev); in soc15_program_aspm()
968 adev->nbio.funcs->set_reg_remap(adev); in soc15_common_early_init()
1244 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); in soc15_common_late_init()
1280 adev->nbio.funcs->sdma_doorbell_range(adev, i, in soc15_sdma_doorbell_range_init()
1294 adev->nbio.funcs->init_registers(adev); in soc15_common_hw_init()
1299 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in soc15_common_hw_init()
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H A Dsoc21.c229 return adev->nbio.funcs->get_memsize(adev); in soc21_get_config_memsize()
358 u32 memsize = adev->nbio.funcs->get_memsize(adev);
445 if (adev->nbio.funcs->program_aspm) in soc21_program_aspm()
446 adev->nbio.funcs->program_aspm(adev); in soc21_program_aspm()
563 adev->nbio.funcs->set_reg_remap(adev); in soc21_common_early_init()
818 if (adev->nbio.ras && in soc21_common_late_init()
819 adev->nbio.ras_err_event_athub_irq.funcs) in soc21_common_late_init()
824 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); in soc21_common_late_init()
830 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); in soc21_common_late_init()
852 adev->nbio.funcs->init_registers(adev); in soc21_common_hw_init()
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H A Dnv.c308 return adev->nbio.funcs->get_memsize(adev); in nv_get_config_memsize()
430 u32 memsize = adev->nbio.funcs->get_memsize(adev); in nv_asic_mode2_reset()
518 if (adev->nbio.funcs->program_aspm) in nv_program_aspm()
519 adev->nbio.funcs->program_aspm(adev); in nv_program_aspm()
610 if (adev->nbio.funcs->enable_aspm && in nv_update_umd_stable_pstate()
612 adev->nbio.funcs->enable_aspm(adev, !enter); in nv_update_umd_stable_pstate()
641 adev->nbio.funcs->set_reg_remap(adev); in nv_common_early_init()
971 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); in nv_common_late_init()
990 if (adev->nbio.funcs->apply_lc_spc_mode_wa) in nv_common_hw_init()
991 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); in nv_common_hw_init()
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H A Damdgpu_device.c938 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); in amdgpu_device_indirect_rreg()
939 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); in amdgpu_device_indirect_rreg()
962 if (unlikely(!adev->nbio.funcs)) { in amdgpu_device_indirect_rreg_ext()
966 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); in amdgpu_device_indirect_rreg_ext()
967 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); in amdgpu_device_indirect_rreg_ext()
971 if (unlikely(!adev->nbio.funcs)) in amdgpu_device_indirect_rreg_ext()
974 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); in amdgpu_device_indirect_rreg_ext()
1021 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); in amdgpu_device_indirect_rreg64()
1022 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); in amdgpu_device_indirect_rreg64()
1051 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); in amdgpu_device_indirect_rreg64_ext()
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H A Damdgpu_discovery.c2753 adev->nbio.funcs = &nbio_v6_1_funcs; in amdgpu_discovery_set_ip_blocks()
2754 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2759 adev->nbio.funcs = &nbio_v7_0_funcs; in amdgpu_discovery_set_ip_blocks()
2760 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2765 adev->nbio.funcs = &nbio_v7_4_funcs; in amdgpu_discovery_set_ip_blocks()
2766 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2769 adev->nbio.funcs = &nbio_v7_9_funcs; in amdgpu_discovery_set_ip_blocks()
2770 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2775 adev->nbio.funcs = &nbio_v7_11_funcs; in amdgpu_discovery_set_ip_blocks()
2776 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
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H A Damdgpu_bios.c532 if (adev->nbio.funcs && in amdgpu_soc15_read_bios_from_rom()
533 adev->nbio.funcs->get_rom_offset) { in amdgpu_soc15_read_bios_from_rom()
534 rom_offset = adev->nbio.funcs->get_rom_offset(adev); in amdgpu_soc15_read_bios_from_rom()
H A Dnbif_v6_3_1.c582 adev->nbio.ras_err_event_athub_irq.funcs = in nbif_v6_3_1_init_ras_err_event_athub_interrupt()
584 adev->nbio.ras_err_event_athub_irq.num_types = 1; in nbif_v6_3_1_init_ras_err_event_athub_interrupt()
591 &adev->nbio.ras_err_event_athub_irq); in nbif_v6_3_1_init_ras_err_event_athub_interrupt()
H A Dnbio_v4_3.c619 adev->nbio.ras_err_event_athub_irq.funcs = in nbio_v4_3_init_ras_err_event_athub_interrupt()
621 adev->nbio.ras_err_event_athub_irq.num_types = 1; in nbio_v4_3_init_ras_err_event_athub_interrupt()
627 &adev->nbio.ras_err_event_athub_irq); in nbio_v4_3_init_ras_err_event_athub_interrupt()
H A Damdgpu_ras.c2172 if (adev->nbio.ras && in amdgpu_ras_interrupt_fatal_error_handler()
2173 adev->nbio.ras->handle_ras_controller_intr_no_bifring) in amdgpu_ras_interrupt_fatal_error_handler()
2174 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev); in amdgpu_ras_interrupt_fatal_error_handler()
2176 if (adev->nbio.ras && in amdgpu_ras_interrupt_fatal_error_handler()
2177 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring) in amdgpu_ras_interrupt_fatal_error_handler()
2178 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev); in amdgpu_ras_interrupt_fatal_error_handler()
3914 adev->nbio.ras = &nbio_v7_4_ras; in amdgpu_ras_init()
3924 adev->nbio.ras = &nbio_v4_3_ras; in amdgpu_ras_init()
3935 adev->nbio.ras = &nbif_v6_3_1_ras; in amdgpu_ras_init()
3940 adev->nbio.ras = &nbio_v7_9_ras; in amdgpu_ras_init()
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H A Dgmc_v9_0.c1396 if (adev->nbio.funcs->get_memory_partition_mode) in gmc_v9_0_get_memory_partition()
1397 mode = adev->nbio.funcs->get_memory_partition_mode(adev, in gmc_v9_0_get_memory_partition()
1433 if (adev->nbio.funcs && adev->nbio.funcs->is_nps_switch_requested && in gmc_v9_0_need_reset_on_init()
1434 adev->nbio.funcs->is_nps_switch_requested(adev)) { in gmc_v9_0_need_reset_on_init()
1750 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; in gmc_v9_0_mc_init()
H A Dvega10_ih.c273 adev->nbio.funcs->ih_control(adev); in vega10_ih_irq_init()
293 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, in vega10_ih_irq_init()
H A Dih_v7_0.c306 adev->nbio.funcs->ih_control(adev); in ih_v7_0_irq_init()
327 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, in ih_v7_0_irq_init()
H A Dnavi10_ih.c329 adev->nbio.funcs->ih_control(adev); in navi10_ih_irq_init()
361 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, in navi10_ih_irq_init()
H A Dvega20_ih.c319 adev->nbio.funcs->ih_control(adev); in vega20_ih_irq_init()
356 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, in vega20_ih_irq_init()
H A Dih_v6_0.c334 adev->nbio.funcs->ih_control(adev); in ih_v6_0_irq_init()
355 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, in ih_v6_0_irq_init()
H A Dih_v6_1.c306 adev->nbio.funcs->ih_control(adev); in ih_v6_1_irq_init()
327 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, in ih_v6_1_irq_init()
H A Dsdma_v7_0.c357 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; in sdma_v7_0_ring_emit_hdp_flush()
364 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); in sdma_v7_0_ring_emit_hdp_flush()
365 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); in sdma_v7_0_ring_emit_hdp_flush()
588 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, in sdma_v7_0_gfx_resume_instance()
H A Dsdma_v6_0.c325 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; in sdma_v6_0_ring_emit_hdp_flush()
332 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); in sdma_v6_0_ring_emit_hdp_flush()
333 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); in sdma_v6_0_ring_emit_hdp_flush()
564 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, in sdma_v6_0_gfx_resume_instance()
H A Dsdma_v5_2.c340 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; in sdma_v5_2_ring_emit_hdp_flush()
350 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); in sdma_v5_2_ring_emit_hdp_flush()
351 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); in sdma_v5_2_ring_emit_hdp_flush()
624 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, in sdma_v5_2_gfx_resume_instance()
H A Djpeg_v3_0.c150 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, in jpeg_v3_0_hw_init()
H A Dsdma_v5_0.c522 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; in sdma_v5_0_ring_emit_hdp_flush()
532 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); in sdma_v5_0_ring_emit_hdp_flush()
533 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); in sdma_v5_0_ring_emit_hdp_flush()
811 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, in sdma_v5_0_gfx_resume_instance()
H A Dvpe_v6_1.c258 adev->nbio.funcs->vpe_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index + i*4, 4); in vpe_v6_1_ring_start()
/linux/drivers/block/xen-blkback/
H A Dblkback.c1299 int i, nbio = 0; in dispatch_rw_block_io() local
1437 biolist[nbio++] = bio; in dispatch_rw_block_io()
1452 biolist[nbio++] = bio; in dispatch_rw_block_io()
1457 atomic_set(&pending_req->pendcnt, nbio); in dispatch_rw_block_io()
1460 for (i = 0; i < nbio; i++) in dispatch_rw_block_io()

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