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Searched refs:nbio (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_nbio.c30 if (!adev->nbio.ras) in amdgpu_nbio_ras_sw_init()
33 ras = adev->nbio.ras; in amdgpu_nbio_ras_sw_init()
43 adev->nbio.ras_if = &ras->ras_block.ras_comm; in amdgpu_nbio_ras_sw_init()
50 if (adev->nbio.funcs && adev->nbio.funcs->get_pcie_replay_count) in amdgpu_nbio_get_pcie_replay_count()
51 return adev->nbio.funcs->get_pcie_replay_count(adev); in amdgpu_nbio_get_pcie_replay_count()
60 (!adev->nbio.funcs || !adev->nbio.funcs->get_pcie_replay_count)) in amdgpu_nbio_is_replay_cnt_supported()
74 r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0); in amdgpu_nbio_ras_late_init()
77 r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); in amdgpu_nbio_ras_late_init()
H A Dsoc15.c342 return adev->nbio.funcs->get_memsize(adev); in soc15_get_config_memsize()
513 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); in soc15_asic_baco_reset()
521 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); in soc15_asic_baco_reset()
703 if (adev->nbio.funcs->program_aspm) in soc15_program_aspm()
704 adev->nbio.funcs->program_aspm(adev); in soc15_program_aspm()
964 adev->nbio.funcs->set_reg_remap(adev); in soc15_common_early_init()
1242 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); in soc15_common_late_init()
1278 adev->nbio.funcs->sdma_doorbell_range(adev, i, in soc15_sdma_doorbell_range_init()
1292 adev->nbio.funcs->init_registers(adev); in soc15_common_hw_init()
1297 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in soc15_common_hw_init()
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H A Damdgpu_discovery.c2968 adev->nbio.funcs = &nbio_v6_1_funcs; in amdgpu_discovery_set_ip_blocks()
2969 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2974 adev->nbio.funcs = &nbio_v7_0_funcs; in amdgpu_discovery_set_ip_blocks()
2975 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2980 adev->nbio.funcs = &nbio_v7_4_funcs; in amdgpu_discovery_set_ip_blocks()
2981 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2985 adev->nbio.funcs = &nbio_v7_9_funcs; in amdgpu_discovery_set_ip_blocks()
2986 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2992 adev->nbio.funcs = &nbio_v7_11_funcs; in amdgpu_discovery_set_ip_blocks()
2993 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
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H A Dhdp_v5_2.c44 if (adev->nbio.funcs->get_memsize) in hdp_v5_2_flush_hdp()
45 adev->nbio.funcs->get_memsize(adev); in hdp_v5_2_flush_hdp()
H A Damdgpu_ras.c2388 if (adev->nbio.ras && in amdgpu_ras_interrupt_fatal_error_handler()
2389 adev->nbio.ras->handle_ras_controller_intr_no_bifring) in amdgpu_ras_interrupt_fatal_error_handler()
2390 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev); in amdgpu_ras_interrupt_fatal_error_handler()
2392 if (adev->nbio.ras && in amdgpu_ras_interrupt_fatal_error_handler()
2393 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring) in amdgpu_ras_interrupt_fatal_error_handler()
2394 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev); in amdgpu_ras_interrupt_fatal_error_handler()
4309 adev->nbio.ras = &nbio_v7_4_ras; in amdgpu_ras_init()
4319 adev->nbio.ras = &nbio_v4_3_ras; in amdgpu_ras_init()
4330 adev->nbio.ras = &nbif_v6_3_1_ras; in amdgpu_ras_init()
4335 adev->nbio.ras = &nbio_v7_9_ras; in amdgpu_ras_init()
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H A Damdgpu_mes.c535 hdp_flush_req_offset = adev->nbio.funcs->get_hdp_flush_req_offset(adev); in amdgpu_mes_hdp_flush()
536 hdp_flush_done_offset = adev->nbio.funcs->get_hdp_flush_done_offset(adev); in amdgpu_mes_hdp_flush()
537 ref_and_mask = adev->nbio.hdp_flush_reg->ref_and_mask_cp0; in amdgpu_mes_hdp_flush()
H A Dgmc_v9_0.c1380 if (adev->nbio.funcs && adev->nbio.funcs->is_nps_switch_requested && in gmc_v9_0_need_reset_on_init()
1381 adev->nbio.funcs->is_nps_switch_requested(adev)) { in gmc_v9_0_need_reset_on_init()
1706 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; in gmc_v9_0_mc_init()
H A Dsdma_v6_0.c328 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; in sdma_v6_0_ring_emit_hdp_flush()
335 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); in sdma_v6_0_ring_emit_hdp_flush()
336 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); in sdma_v6_0_ring_emit_hdp_flush()
565 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, in sdma_v6_0_gfx_resume_instance()
H A Damdgpu_gmc.c1479 if (adev->nbio.funcs && in amdgpu_gmc_get_memory_partition()
1480 adev->nbio.funcs->get_memory_partition_mode) in amdgpu_gmc_get_memory_partition()
1481 mode = adev->nbio.funcs->get_memory_partition_mode(adev, in amdgpu_gmc_get_memory_partition()
H A Daqua_vanjaram.c125 if (adev->nbio.funcs->get_compute_partition_mode) { in aqua_vanjaram_query_partition_mode()
126 mode = adev->nbio.funcs->get_compute_partition_mode(adev); in aqua_vanjaram_query_partition_mode()
H A Dvpe_v6_1.c258 adev->nbio.funcs->vpe_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index + i*4, 4); in vpe_v6_1_ring_start()
H A Dumsch_mm_v4_0.c225 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, in umsch_mm_v4_0_ring_start()
H A Dgmc_v12_0.c714 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; in gmc_v12_0_mc_init()
H A Dgmc_v11_0.c704 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; in gmc_v11_0_mc_init()
H A Dgmc_v10_0.c706 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; in gmc_v10_0_mc_init()
H A Djpeg_v5_0_1.c278 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, in jpeg_v5_0_1_hw_init()
H A Dgfx_v12_0.c3678 if (adev->nbio.funcs->gc_doorbell_init) in gfx_v12_0_hw_init()
3679 adev->nbio.funcs->gc_doorbell_init(adev); in gfx_v12_0_hw_init()
4390 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; in gfx_v12_0_ring_emit_hdp_flush()
4410 adev->nbio.funcs->get_hdp_flush_req_offset(adev), in gfx_v12_0_ring_emit_hdp_flush()
4411 adev->nbio.funcs->get_hdp_flush_done_offset(adev), in gfx_v12_0_ring_emit_hdp_flush()
H A Dgfx_v11_0.c4816 if (adev->nbio.funcs->gc_doorbell_init) in gfx_v11_0_hw_init()
4817 adev->nbio.funcs->gc_doorbell_init(adev); in gfx_v11_0_hw_init()
5834 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; in gfx_v11_0_ring_emit_hdp_flush()
5854 adev->nbio.funcs->get_hdp_flush_req_offset(adev), in gfx_v11_0_ring_emit_hdp_flush()
5855 adev->nbio.funcs->get_hdp_flush_done_offset(adev), in gfx_v11_0_ring_emit_hdp_flush()
H A Damdgpu.h1101 struct amdgpu_nbio nbio; member
H A Dvcn_v5_0_1.c282 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, in vcn_v5_0_1_hw_init_inst()
H A Dvcn_v4_0_5.c300 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, in vcn_v4_0_5_hw_init()
H A Dvcn_v4_0_3.c302 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, in vcn_v4_0_3_hw_init_inst()
H A Dvcn_v4_0.c346 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, in vcn_v4_0_hw_init()
H A Dvcn_v3_0.c414 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, in vcn_v3_0_hw_init()