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Searched refs:mtk_phy_set_bits (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt2701.c55 mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); in mtk_hdmi_pll_prepare()
57 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); in mtk_hdmi_pll_prepare()
58 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); in mtk_hdmi_pll_prepare()
60 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN); in mtk_hdmi_pll_prepare()
61 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); in mtk_hdmi_pll_prepare()
62 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); in mtk_hdmi_pll_prepare()
64 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); in mtk_hdmi_pll_prepare()
65 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); in mtk_hdmi_pll_prepare()
66 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); in mtk_hdmi_pll_prepare()
67 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); in mtk_hdmi_pll_prepare()
[all …]
H A Dphy-mtk-ufs.c64 mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_PWR_ON); in ufs_mtk_phy_set_active()
72 mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_PWR_ON); in ufs_mtk_phy_set_active()
80 mtk_phy_set_bits(mmio + MP_LN_DIG_RX_AC, RX_SQ_EN); in ufs_mtk_phy_set_active()
95 mtk_phy_set_bits(mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC); in ufs_mtk_phy_set_deep_hibern()
98 mtk_phy_set_bits(mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN); in ufs_mtk_phy_set_deep_hibern()
102 mtk_phy_set_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN); in ufs_mtk_phy_set_deep_hibern()
103 mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_ISO_EN); in ufs_mtk_phy_set_deep_hibern()
106 mtk_phy_set_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON); in ufs_mtk_phy_set_deep_hibern()
110 mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN); in ufs_mtk_phy_set_deep_hibern()
111 mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN); in ufs_mtk_phy_set_deep_hibern()
[all …]
H A Dphy-mtk-mipi-dsi-mt8196.c107 mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); in mtk_mipi_tx_pll_enable()
117 mtk_phy_set_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN); in mtk_mipi_tx_pll_enable()
130 mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); in mtk_mipi_tx_pll_disable()
178 mtk_phy_set_bits(base + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); in mtk_mipi_tx_power_on_signal()
187 mtk_phy_set_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_off_signal()
188 mtk_phy_set_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_off_signal()
189 mtk_phy_set_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_off_signal()
190 mtk_phy_set_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_off_signal()
191 mtk_phy_set_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_off_signal()
H A Dphy-mtk-io.h22 static inline void mtk_phy_set_bits(void __iomem *reg, u32 bits) in mtk_phy_set_bits() function
H A Dphy-mtk-mipi-csi-0-5.c136 mtk_phy_set_bits(base + MIPI_RX_ANA40_CSIXA, 0x90); in mtk_mipi_phy_power_on()