Searched refs:mtk_phy_clear_bits (Results 1 – 3 of 3) sorted by relevance
| /linux/drivers/phy/mediatek/ |
| H A D | phy-mtk-ufs.c | 66 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON); in ufs_mtk_phy_set_active() 69 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN); in ufs_mtk_phy_set_active() 70 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN); in ufs_mtk_phy_set_active() 74 mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON); in ufs_mtk_phy_set_active() 77 mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_ISO_EN); in ufs_mtk_phy_set_active() 78 mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN); in ufs_mtk_phy_set_active() 82 mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN); in ufs_mtk_phy_set_active() 88 mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC); in ufs_mtk_phy_set_active() 100 mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_AC, RX_SQ_EN); in ufs_mtk_phy_set_deep_hibern() 108 mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_PWR_ON); in ufs_mtk_phy_set_deep_hibern() [all …]
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| H A D | phy-mtk-xsphy.c | 154 mtk_phy_clear_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); in u2_phy_slew_rate_calibrate() 157 mtk_phy_clear_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); in u2_phy_slew_rate_calibrate() 176 mtk_phy_clear_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN); in u2_phy_slew_rate_calibrate() 185 mtk_phy_clear_bits(pbase + XSP_USBPHYACR6, P2A6_RG_BC11_SW_EN); in u2_phy_instance_init() 211 mtk_phy_clear_bits(pbase + XSP_USBPHYACR6, P2A6_RG_OTG_VBUSCMP_EN); in u2_phy_instance_power_off()
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| H A D | phy-mtk-io.h | 14 static inline void mtk_phy_clear_bits(void __iomem *reg, u32 bits) in mtk_phy_clear_bits() function
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