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Searched refs:mtk_phy_clear_bits (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt2701.c56 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); in mtk_hdmi_pll_prepare()
77 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); in mtk_hdmi_pll_unprepare()
78 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); in mtk_hdmi_pll_unprepare()
79 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); in mtk_hdmi_pll_unprepare()
80 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); in mtk_hdmi_pll_unprepare()
82 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); in mtk_hdmi_pll_unprepare()
83 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); in mtk_hdmi_pll_unprepare()
84 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN); in mtk_hdmi_pll_unprepare()
86 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); in mtk_hdmi_pll_unprepare()
87 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); in mtk_hdmi_pll_unprepare()
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H A Dphy-mtk-ufs.c65 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON); in ufs_mtk_phy_set_active()
68 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN); in ufs_mtk_phy_set_active()
69 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN); in ufs_mtk_phy_set_active()
73 mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON); in ufs_mtk_phy_set_active()
76 mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_ISO_EN); in ufs_mtk_phy_set_active()
77 mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN); in ufs_mtk_phy_set_active()
81 mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN); in ufs_mtk_phy_set_active()
87 mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC); in ufs_mtk_phy_set_active()
99 mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_AC, RX_SQ_EN); in ufs_mtk_phy_set_deep_hibern()
107 mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_PWR_ON); in ufs_mtk_phy_set_deep_hibern()
[all …]
H A Dphy-mtk-mipi-dsi-mt8196.c108 mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN); in mtk_mipi_tx_pll_enable()
112 mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); in mtk_mipi_tx_pll_enable()
128 mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN); in mtk_mipi_tx_pll_disable()
131 mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); in mtk_mipi_tx_pll_disable()
163 mtk_phy_clear_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_on_signal()
164 mtk_phy_clear_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_on_signal()
165 mtk_phy_clear_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_on_signal()
166 mtk_phy_clear_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_on_signal()
167 mtk_phy_clear_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_on_signal()
H A Dphy-mtk-io.h14 static inline void mtk_phy_clear_bits(void __iomem *reg, u32 bits) in mtk_phy_clear_bits() function