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Searched refs:mtk_ddp_write_mask (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/mediatek/
H A Dmtk_mdp_rdma.c152 mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | VAL_PRE_ULTRA_EN_ENABLE << 16 | in mtk_mdp_rdma_fifo_config()
164 mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg, in mtk_mdp_rdma_start()
172 mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, in mtk_mdp_rdma_stop()
189 mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv->cmdq_reg, priv->regs, in mtk_mdp_rdma_config()
191 mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv->cmdq_reg, priv->regs, in mtk_mdp_rdma_config()
195 mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv->cmdq_reg, in mtk_mdp_rdma_config()
198 mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, in mtk_mdp_rdma_config()
201 mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv->regs, in mtk_mdp_rdma_config()
204 mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, priv->regs, in mtk_mdp_rdma_config()
207 mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_COMP_CON, in mtk_mdp_rdma_config()
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H A Dmtk_ddp_comp.c95 void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, in mtk_ddp_write_mask() function
197 mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs, in mtk_dsc_config()
199 mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs, in mtk_dsc_config()
201 mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs, in mtk_dsc_config()
210 mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN); in mtk_dsc_start()
H A Dmtk_ethdr.c210 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON, in mtk_ethdr_layer_config()
258 mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs, in mtk_ethdr_config()
H A Dmtk_ddp_comp.h362 void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,