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Searched refs:mtctl (Results 1 – 19 of 19) sorted by relevance

/linux/arch/parisc/kernel/
H A Dhead.S76 mtctl %r10,%cr11
115 mtctl %r4,%cr24 /* Initialize kernel root pointer */
116 mtctl %r4,%cr25 /* Initialize user root pointer */
168 mtctl %r6,%cr30
269 mtctl %r6,%cr30 /* restore task thread info */
289 mtctl %r0,%cr8
290 mtctl %r0,%cr9
291 mtctl %r0,%cr12
292 mtctl %r0,%cr13
305 mtctl %r10,%cr11
[all …]
H A Dreal2.S107 # define POP_CR(r, where) LDREG,mb -REG_SZ(where), %r1 ! mtctl %r1, r
157 mtctl %r0, %cr17 /* Clear IIASQ tail */
158 mtctl %r0, %cr17 /* Clear IIASQ head */
159 mtctl %r1, %cr18 /* IIAOQ head */
161 mtctl %r1, %cr18 /* IIAOQ tail */
163 mtctl %r1, %cr22
194 mtctl %r0, %cr17 /* Clear IIASQ tail */
195 mtctl %r0, %cr17 /* Clear IIASQ head */
196 mtctl %r1, %cr18 /* IIAOQ head */
198 mtctl %r1, %cr18 /* IIAOQ tail */
[all …]
H A Drelocate_kernel.S62 mtctl %r0, %cr17 /* IIASQ */
63 mtctl %r0, %cr17 /* IIASQ */
64 mtctl %r1, %cr18 /* IIAOQ */
66 mtctl %r1, %cr18 /* IIAOQ */
69 mtctl %r1, %cr22 /* IPSW */
71 mtctl %r0, %cr22 /* IPSW */
133 mtctl %r0, %cr15
H A Dhpmc.S126 mtctl %r4,ipsw
127 mtctl %r0,pcsq
128 mtctl %r0,pcsq
130 mtctl %r4,pcoq
132 mtctl %r4,pcoq
235 mtctl %r4,%cr24 /* Initialize kernel root pointer */
236 mtctl %r4,%cr25 /* Initialize user root pointer */
H A Dtoc_asm.S46 mtctl %r4,%cr24
47 mtctl %r4,%cr25
H A Dpacache.S52 mtctl %r0, %cr17 /* Clear IIASQ tail */
53 mtctl %r0, %cr17 /* Clear IIASQ head */
54 mtctl %r1, %cr18 /* IIAOQ head */
56 mtctl %r1, %cr18 /* IIAOQ tail */
58 mtctl %r1, %ipsw
164 mtctl %r0, %cr17 /* Clear IIASQ tail */
165 mtctl %r0, %cr17 /* Clear IIASQ head */
166 mtctl %r1, %cr18 /* IIAOQ head */
168 mtctl %r1, %cr18 /* IIAOQ tail */
171 mtctl %r1, %ipsw /* restore I-bit (entire PSW) */
[all …]
H A Dsmp.c482 mtctl(~0UL, CR_EIRR); in __cpu_disable()
484 mtctl(0, CR_EIRR); in __cpu_disable()
H A Dperf_asm.S43 mtctl %r26,ccr ; turn on performance coprocessor
48 mtctl %r26,ccr ; turn off performance coprocessor
69 mtctl %r26,ccr ; turn on performance coprocessor
74 mtctl %r26,ccr ; turn off performance coprocessor
H A Dirq.c81 mtctl(mask, 23); in cpu_ack_irq()
568 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */ in init_IRQ()
H A Dcache.c463 mtctl(pgd_lock, 28); in get_upa()
465 mtctl(pgd, 25); in get_upa()
467 mtctl(prot, 8); in get_upa()
H A Dtime.c36 mtctl(new_cr16, 16); in parisc_timer_next_event()
H A Dsetup.c293 mtctl(coproc_cfg.ccr_functional, 10); in start_parisc()
H A Dprocessor.c336 mtctl(coproc_cfg.ccr_functional, 10); /* 10 == Coprocessor Control Reg */ in init_per_cpu()
H A Dentry.S780 mtctl %r25,%cr30
783 mtctl %r0, %cr0 /* Needed for single stepping */
1679 mtctl %r3, %cr27
1832 mtctl %r2,%cr0 /* for immediate trap */
2068 mtctl %rp, %cr11
H A Dsignal.c342 mtctl(-1, 0); in setup_rt_frame()
H A Dsyscall.S121 mtctl %r26, %cr27 /* move arg0 to the control register */
/linux/arch/parisc/include/asm/
H A Dmmu_context.h47 mtctl(__space_to_prot(context), 8); in load_context()
58 mtctl(__pa(__ldcw_align(&pgd_lock->rlock.raw_lock)), 28); in switch_mm_irqs_off()
60 mtctl(__pa(next->pgd), 25); in switch_mm_irqs_off()
H A Dspecial_insns.h76 #define mtctl(gr, cr) \ macro
82 #define set_eiem(val) mtctl(val, CR_EIEM)
H A Dassembly.h207 #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
412 mtctl %r3, %cr27
456 mtctl %r3, %cr27
472 mtctl %r0, %cr17
476 mtctl %r0, %cr18
558 mtctl %r0, %cr17 /* Clear IIASQ tail */
559 mtctl %r0, %cr17 /* Clear IIASQ head */
560 mtctl %r1, %ipsw
562 mtctl %r1, %cr18 /* Set IIAOQ tail */
564 mtctl %r1, %cr18 /* Set IIAOQ head */