Searched refs:msrval (Results 1 – 6 of 6) sorted by relevance
112 u64 msrval; in ifs_init() local119 if (rdmsrq_safe(MSR_IA32_CORE_CAPS, &msrval)) in ifs_init()122 if (!(msrval & MSR_IA32_CORE_CAPS_INTEGRITY_CAPS)) in ifs_init()125 if (rdmsrq_safe(MSR_INTEGRITY_CAPS, &msrval)) in ifs_init()133 if (!(msrval & BIT(ifs_devices[i].test_caps->integrity_cap_bit))) in ifs_init()136 msrval); in ifs_init()
485 u64 msrval; in wrss_control() local503 rdmsrq(MSR_IA32_U_CET, msrval); in wrss_control()507 msrval |= CET_WRSS_EN; in wrss_control()510 if (!(msrval & CET_WRSS_EN)) in wrss_control()513 msrval &= ~CET_WRSS_EN; in wrss_control()516 wrmsrq(MSR_IA32_U_CET, msrval); in wrss_control()
159 u64 msrval; in topoext_fixup() local170 rdmsrq(MSR_AMD64_CPUID_EXT_FEAT, msrval); in topoext_fixup()171 if (msrval & MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT) { in topoext_fixup()
92 u64 msrval; in resctrl_arch_mon_event_config_read() local99 rdmsrq(MSR_IA32_EVT_CFG_BASE + index, msrval); in resctrl_arch_mon_event_config_read()102 config_info->mon_config = msrval & MAX_EVT_CONFIG_BITS; in resctrl_arch_mon_event_config_read()
1901 u64 msrval; in __mcheck_cpu_init_prepare_banks() local1925 rdmsrq(mca_msr_reg(i, MCA_CTL), msrval); in __mcheck_cpu_init_prepare_banks()1926 b->init = !!msrval; in __mcheck_cpu_init_prepare_banks()
339 msrval = jd.get('MSRValue')