| /linux/drivers/gpu/drm/msm/ |
| H A D | msm_gpu.h | 49 int (*get_param)(struct msm_gpu *gpu, struct msm_context *ctx,
51 int (*set_param)(struct msm_gpu *gpu, struct msm_context *ctx,
53 int (*hw_init)(struct msm_gpu *gpu);
58 int (*ucode_load)(struct msm_gpu *gpu);
60 int (*pm_suspend)(struct msm_gpu *gpu);
61 int (*pm_resume)(struct msm_gpu *gpu);
62 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
63 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
64 irqreturn_t (*irq)(struct msm_gpu *irq);
65 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
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| H A D | msm_gpu.c | 25 static int enable_pwrrail(struct msm_gpu *gpu) in enable_pwrrail()
49 static int disable_pwrrail(struct msm_gpu *gpu) in disable_pwrrail()
58 static int enable_clk(struct msm_gpu *gpu) in enable_clk()
70 static int disable_clk(struct msm_gpu *gpu) in disable_clk()
88 static int enable_axi(struct msm_gpu *gpu) in enable_axi()
93 static int disable_axi(struct msm_gpu *gpu) in disable_axi()
99 int msm_gpu_pm_resume(struct msm_gpu *gpu) in msm_gpu_pm_resume()
125 int msm_gpu_pm_suspend(struct msm_gpu *gpu) in msm_gpu_pm_suspend()
151 void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_context *ctx, in msm_gpu_show_fdinfo()
159 int msm_gpu_hw_init(struct msm_gpu *gpu) in msm_gpu_hw_init()
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| H A D | msm_mmu.h | 14 struct msm_gpu;
78 struct msm_mmu *msm_iommu_gpu_new(struct device *dev, struct msm_gpu *gpu, unsigned long quirks);
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| H A D | msm_debugfs.c | 37 struct msm_gpu *gpu = priv->gpu; in msm_gpu_show()
57 struct msm_gpu *gpu = priv->gpu; in msm_gpu_release()
72 struct msm_gpu *gpu = priv->gpu; in msm_gpu_open()
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| H A D | msm_perf.c | 61 struct msm_gpu *gpu = priv->gpu; in refill_buf()
155 struct msm_gpu *gpu = priv->gpu; in perf_open()
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| H A D | msm_gem_submit.c | 33 struct msm_gpu *gpu, in submit_create()
556 struct msm_gpu *gpu = priv->gpu; in msm_ioctl_gem_submit()
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| H A D | msm_gem.h | 436 struct msm_gpu *gpu;
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| /linux/drivers/gpu/drm/msm/adreno/ |
| H A D | a6xx_gpu.h | 274 void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu);
276 void a6xx_preempt_init(struct msm_gpu *gpu);
277 void a6xx_preempt_hw_init(struct msm_gpu *gpu);
278 void a6xx_preempt_trigger(struct msm_gpu *gpu);
279 void a6xx_preempt_irq(struct msm_gpu *gpu);
280 void a6xx_preempt_fini(struct msm_gpu *gpu);
281 int a6xx_preempt_submitqueue_setup(struct msm_gpu *gpu,
283 void a6xx_preempt_submitqueue_close(struct msm_gpu *gpu,
304 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
306 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu);
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| H A D | a5xx_gpu.h | 54 void a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor);
138 int a5xx_power_init(struct msm_gpu *gpu);
139 void a5xx_gpmu_ucode_init(struct msm_gpu *gpu);
141 static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs, in spin_usecs()
157 bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
158 void a5xx_set_hwcg(struct msm_gpu *gpu, bool state);
160 void a5xx_preempt_init(struct msm_gpu *gpu);
161 void a5xx_preempt_hw_init(struct msm_gpu *gpu);
162 void a5xx_preempt_trigger(struct msm_gpu *gpu);
163 void a5xx_preempt_irq(struct msm_gpu *gpu);
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| H A D | adreno_gpu.h | 81 struct msm_gpu *(*init)(struct drm_device *dev);
82 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
205 struct msm_gpu base;
608 u64 adreno_private_vm_size(struct msm_gpu *gpu);
609 int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx,
611 int adreno_set_param(struct msm_gpu *gpu, struct msm_context *ctx,
615 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
617 int adreno_hw_init(struct msm_gpu *gpu);
618 void adreno_recover(struct msm_gpu *gpu);
619 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
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| H A D | a4xx_gpu.c | 22 static void a4xx_dump(struct msm_gpu *gpu);
23 static bool a4xx_idle(struct msm_gpu *gpu);
25 static void a4xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a4xx_submit()
76 static void a4xx_enable_hwcg(struct msm_gpu *gpu) in a4xx_enable_hwcg()
156 static bool a4xx_me_init(struct msm_gpu *gpu) in a4xx_me_init()
183 static int a4xx_hw_init(struct msm_gpu *gpu) in a4xx_hw_init()
350 static void a4xx_recover(struct msm_gpu *gpu) in a4xx_recover()
371 static void a4xx_destroy(struct msm_gpu *gpu) in a4xx_destroy()
385 static bool a4xx_idle(struct msm_gpu *gpu) in a4xx_idle()
402 static irqreturn_t a4xx_irq(struct msm_gpu *gpu) in a4xx_irq()
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| H A D | a8xx_gpu.c | 19 static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice) in a8xx_aperture_slice_set()
35 static void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) in a8xx_aperture_acquire()
45 static void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags) in a8xx_aperture_release()
53 static void a8xx_aperture_clear(struct msm_gpu *gpu) in a8xx_aperture_clear()
61 static void a8xx_write_pipe(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 offset, u32 data) in a8xx_write_pipe()
70 static u32 a8xx_read_pipe_slice(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice, u32 offset) in a8xx_read_pipe_slice()
85 void a8xx_gpu_get_slice_info(struct msm_gpu *gpu) in a8xx_gpu_get_slice_info()
120 static inline bool _a8xx_check_idle(struct msm_gpu *gpu) in _a8xx_check_idle()
138 static bool a8xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a8xx_idle()
158 void a8xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a8xx_flush()
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| H A D | a2xx_gpu.c | 10 static void a2xx_dump(struct msm_gpu *gpu);
11 static bool a2xx_idle(struct msm_gpu *gpu);
13 static void a2xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a2xx_submit()
54 static bool a2xx_me_init(struct msm_gpu *gpu) in a2xx_me_init()
108 static int a2xx_hw_init(struct msm_gpu *gpu) in a2xx_hw_init()
266 static void a2xx_recover(struct msm_gpu *gpu) in a2xx_recover()
287 static void a2xx_destroy(struct msm_gpu *gpu) in a2xx_destroy()
299 static bool a2xx_idle(struct msm_gpu *gpu) in a2xx_idle()
317 static irqreturn_t a2xx_irq(struct msm_gpu *gpu) in a2xx_irq()
448 static void a2xx_dump(struct msm_gpu *gpu) in a2xx_dump()
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| H A D | a5xx_gpu.c | 17 static void a5xx_dump(struct msm_gpu *gpu);
21 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_shadow_rptr()
33 void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in a5xx_flush()
66 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a5xx_submit_in_rb()
127 static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a5xx_submit()
446 void a5xx_set_hwcg(struct msm_gpu *gpu, bool state) in a5xx_set_hwcg()
477 static int a5xx_me_init(struct msm_gpu *gpu) in a5xx_me_init()
519 static int a5xx_preempt_start(struct msm_gpu *gpu) in a5xx_preempt_start()
582 static int a5xx_ucode_load(struct msm_gpu *gpu) in a5xx_ucode_load()
644 static int a5xx_zap_shader_resume(struct msm_gpu *gpu) in a5xx_zap_shader_resume()
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| H A D | a3xx_gpu.c | 28 static void a3xx_dump(struct msm_gpu *gpu);
29 static bool a3xx_idle(struct msm_gpu *gpu);
31 static void a3xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a3xx_submit()
85 static bool a3xx_me_init(struct msm_gpu *gpu) in a3xx_me_init()
112 static int a3xx_hw_init(struct msm_gpu *gpu) in a3xx_hw_init()
366 static void a3xx_recover(struct msm_gpu *gpu) in a3xx_recover()
387 static void a3xx_destroy(struct msm_gpu *gpu) in a3xx_destroy()
401 static bool a3xx_idle(struct msm_gpu *gpu) in a3xx_idle()
419 static irqreturn_t a3xx_irq(struct msm_gpu *gpu) in a3xx_irq()
474 static void a3xx_dump(struct msm_gpu *gpu) in a3xx_dump()
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| H A D | adreno_device.c | 68 struct msm_gpu *adreno_load_gpu(struct drm_device *dev) in adreno_load_gpu()
72 struct msm_gpu *gpu = NULL; in adreno_load_gpu()
216 struct msm_gpu *gpu; in adreno_bind()
258 struct msm_gpu *gpu = dev_to_gpu(dev); in adreno_unbind()
308 struct msm_gpu *gpu = dev_to_gpu(dev); in adreno_runtime_resume()
315 struct msm_gpu *gpu = dev_to_gpu(dev); in adreno_runtime_suspend()
327 static void suspend_scheduler(struct msm_gpu *gpu) in suspend_scheduler()
349 static void resume_scheduler(struct msm_gpu *gpu) in resume_scheduler()
362 struct msm_gpu *gpu = dev_to_gpu(dev); in adreno_system_suspend()
389 struct msm_gpu *gpu = dev_to_gpu(dev); in adreno_system_resume()
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| H A D | a6xx_gpu.c | 32 static bool fence_status_check(struct msm_gpu *gpu, u32 offset, u32 value, u32 status, u32 mask) in fence_status_check()
53 struct msm_gpu *gpu = &adreno_gpu->base; in fenced_write()
110 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) in _a6xx_check_idle()
128 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_idle()
147 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_shadow_rptr()
160 void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_flush()
328 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a6xx_submit()
452 static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a7xx_submit()
625 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) in a6xx_set_hwcg()
707 static void a6xx_set_cp_protect(struct msm_gpu *gpu) in a6xx_set_cp_protect()
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| H A D | a5xx_preempt.c | 40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring()
84 struct msm_gpu *gpu = &a5xx_gpu->base.base; in a5xx_preempt_timer()
95 void a5xx_preempt_trigger(struct msm_gpu *gpu) in a5xx_preempt_trigger()
175 void a5xx_preempt_irq(struct msm_gpu *gpu) in a5xx_preempt_irq()
217 void a5xx_preempt_hw_init(struct msm_gpu *gpu) in a5xx_preempt_hw_init()
250 struct msm_gpu *gpu = &adreno_gpu->base; in preempt_init_ring()
292 void a5xx_preempt_fini(struct msm_gpu *gpu) in a5xx_preempt_fini()
304 void a5xx_preempt_init(struct msm_gpu *gpu) in a5xx_preempt_init()
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| H A D | a6xx_gpu_state.c | 131 static int a6xx_crashdumper_init(struct msm_gpu *gpu, in a6xx_crashdumper_init()
144 static int a6xx_crashdumper_run(struct msm_gpu *gpu, in a6xx_crashdumper_run()
174 static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset, in debugbus_read()
208 static int cx_debugbus_read(struct msm_gpu *gpu, void __iomem *cxdbg, u32 block, u32 offset, in cx_debugbus_read()
236 static int vbif_debugbus_read(struct msm_gpu *gpu, u32 ctrl0, u32 ctrl1, in vbif_debugbus_read()
260 static void a6xx_get_vbif_debugbus_block(struct msm_gpu *gpu, in a6xx_get_vbif_debugbus_block()
314 static void a6xx_get_debugbus_block(struct msm_gpu *gpu, in a6xx_get_debugbus_block()
332 static void a6xx_get_cx_debugbus_block(struct msm_gpu *gpu, in a6xx_get_cx_debugbus_block()
351 static void a6xx_get_debugbus_blocks(struct msm_gpu *gpu, in a6xx_get_debugbus_blocks()
398 static void a7xx_get_debugbus_blocks(struct msm_gpu *gpu, in a7xx_get_debugbus_blocks()
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| H A D | adreno_gpu.c | 30 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, in zap_shader_load_mdt()
169 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) in adreno_zap_shader_load()
188 adreno_create_vm(struct msm_gpu *gpu, in adreno_create_vm()
195 adreno_iommu_create_vm(struct msm_gpu *gpu, in adreno_iommu_create_vm()
229 u64 adreno_private_vm_size(struct msm_gpu *gpu) in adreno_private_vm_size()
257 struct msm_gpu *gpu = &adreno_gpu->base; in adreno_check_and_reenable_stall()
283 int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, in adreno_fault_handler()
359 int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx, in adreno_get_param()
452 int adreno_set_param(struct msm_gpu *gpu, struct msm_context *ctx, in adreno_set_param()
628 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, in adreno_fw_create_bo()
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| H A D | a6xx_preempt.c | 63 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring()
92 struct msm_gpu *gpu = &a6xx_gpu->base.base; in a6xx_preempt_timer()
143 static void a6xx_preempt_keepalive_vote(struct msm_gpu *gpu, bool on) in a6xx_preempt_keepalive_vote()
154 void a6xx_preempt_irq(struct msm_gpu *gpu) in a6xx_preempt_irq()
205 void a6xx_preempt_hw_init(struct msm_gpu *gpu) in a6xx_preempt_hw_init()
241 void a6xx_preempt_trigger(struct msm_gpu *gpu) in a6xx_preempt_trigger()
358 struct msm_gpu *gpu = &adreno_gpu->base; in preempt_init_ring()
421 void a6xx_preempt_fini(struct msm_gpu *gpu) in a6xx_preempt_fini()
431 void a6xx_preempt_init(struct msm_gpu *gpu) in a6xx_preempt_init()
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| H A D | a2xx_gpummu.c | 16 struct msm_gpu *gpu;
94 struct msm_mmu *a2xx_gpummu_new(struct device *dev, struct msm_gpu *gpu) in a2xx_gpummu_new()
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| H A D | a6xx_gmu.c | 25 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_gmu_fault()
120 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, in a6xx_gmu_set_freq()
216 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) in a6xx_gmu_get_freq()
897 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_gmu_fw_start()
1090 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_gmu_force_off()
1133 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) in a6xx_gmu_set_initial_freq()
1147 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu) in a6xx_gmu_set_initial_bw()
1163 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_gmu_resume()
1344 struct msm_gpu *gpu = &a6xx_gpu->base.base; in a6xx_gmu_stop()
1703 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_gmu_rpmh_votes_init()
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| H A D | a2xx_gpu.h | 24 struct msm_mmu *a2xx_gpummu_new(struct device *dev, struct msm_gpu *gpu);
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| H A D | a6xx_gpu_state.h | 406 static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu);
407 static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu);
414 u32 (*count_fn)(struct msm_gpu *gpu);
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