Home
last modified time | relevance | path

Searched refs:msm_dp_write_p0 (Results 1 – 1 of 1) sorted by relevance

/linux/drivers/gpu/drm/msm/dp/
H A Ddp_panel.c47 static inline void msm_dp_write_p0(struct msm_dp_panel_private *panel, in msm_dp_write_p0() function
370 msm_dp_write_p0(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); in msm_dp_panel_tpg_enable()
371 msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * in msm_dp_panel_tpg_enable()
373 msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * in msm_dp_panel_tpg_enable()
375 msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); in msm_dp_panel_tpg_enable()
376 msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); in msm_dp_panel_tpg_enable()
377 msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); in msm_dp_panel_tpg_enable()
378 msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); in msm_dp_panel_tpg_enable()
379 msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); in msm_dp_panel_tpg_enable()
380 msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); in msm_dp_panel_tpg_enable()
[all …]