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Searched refs:mmio_base (Results 1 – 25 of 104) sorted by relevance

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/linux/drivers/edac/
H A Dal_mc_edac.c57 void __iomem *mmio_base; member
83 eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT); in handle_ce()
88 ecccaddr0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR0); in handle_ce()
89 ecccaddr1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR1); in handle_ce()
90 ecccsyn0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND0); in handle_ce()
91 ecccsyn1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND1); in handle_ce()
92 ecccsyn2 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND2); in handle_ce()
95 al_mc->mmio_base + AL_MC_ECC_CLEAR); in handle_ce()
128 eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT); in handle_ue()
133 eccuaddr0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_ADDR0); in handle_ue()
[all …]
/linux/drivers/ata/
H A Dsata_sil.c253 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; in sil_bmdma_stop()
254 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2; in sil_bmdma_stop() local
279 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; in sil_bmdma_start()
280 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2; in sil_bmdma_start() local
347 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; in sil_set_mode()
348 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode; in sil_set_mode() local
508 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; in sil_interrupt()
516 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2); in sil_interrupt()
537 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; in sil_freeze()
541 writel(0, mmio_base in sil_freeze()
509 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; sil_interrupt() local
538 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; sil_freeze() local
566 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; sil_thaw() local
653 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; sil_init_controller() local
727 void __iomem *mmio_base; sil_init_one() local
[all...]
H A Dpata_pdc2027x.c475 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; in pdc_read_counter()
481 bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; in pdc_read_counter()
482 bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; in pdc_read_counter()
485 bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; in pdc_read_counter()
486 bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; in pdc_read_counter()
516 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; in pdc_adjust_pll()
535 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); in pdc_adjust_pll()
574 iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL); in pdc_adjust_pll()
575 ioread16(mmio_base + PDC_PLL_CTL); /* flush */ in pdc_adjust_pll()
584 pll_ctl = ioread16(mmio_base in pdc_detect_pll_input_clock()
461 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; pdc_read_counter() local
502 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; pdc_adjust_pll() local
585 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; pdc_detect_pll_input_clock() local
690 void __iomem *mmio_base; pdc2027x_init_one() local
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H A Dsata_qstor.c191 u8 __iomem *mmio_base = qs_mmio_base(ap->host); in qs_freeze()
193 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */ in qs_freeze()
199 u8 __iomem *mmio_base = qs_mmio_base(ap->host); in qs_thaw()
202 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */ in qs_thaw()
354 u8 __iomem *mmio_base = qs_mmio_base(host); in qs_intr_pkt() local
357 u32 sff0 = readl(mmio_base + QS_HST_SFF); in qs_intr_pkt()
358 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4); in qs_intr_pkt()
460 void __iomem *mmio_base = qs_mmio_base(ap->host); in qs_port_start() local
461 void __iomem *chan = mmio_base + (ap->port_no * 0x4000); in qs_port_start()
482 void __iomem *mmio_base in qs_host_stop() local
192 u8 __iomem *mmio_base = qs_mmio_base(ap->host); qs_freeze() local
200 u8 __iomem *mmio_base = qs_mmio_base(ap->host); qs_thaw() local
490 void __iomem *mmio_base = host->iomap[QS_MMIO_BAR]; qs_host_init() local
528 qs_set_dma_masks(struct pci_dev * pdev,void __iomem * mmio_base) qs_set_dma_masks() argument
[all...]
H A Dpata_sil680.c340 void __iomem *mmio_base; in sil680_init_one() local
380 mmio_base = host->iomap[SIL680_MMIO_BAR]; in sil680_init_one()
381 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00; in sil680_init_one()
382 host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80; in sil680_init_one()
383 host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a; in sil680_init_one()
384 host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a; in sil680_init_one()
386 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08; in sil680_init_one()
387 host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0; in sil680_init_one()
388 host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca; in sil680_init_one()
389 host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca; in sil680_init_one()
H A Dsata_inic162x.c234 void __iomem *mmio_base; member
268 return hpriv->mmio_base + ap->port_no * PORT_SIZE; in inic_port_base()
426 host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT); in inic_interrupt()
753 static int init_controller(void __iomem *mmio_base, u16 hctl) in init_controller()
763 writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL); in init_controller()
764 readw(mmio_base + HOST_CTL); /* flush */ in init_controller()
768 val = readw(mmio_base + HOST_CTL); in init_controller()
778 void __iomem *port_base = mmio_base + i * PORT_SIZE; in init_controller()
785 writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL); in init_controller()
786 val = readw(mmio_base in init_controller()
752 init_controller(void __iomem * mmio_base,u16 hctl) init_controller() argument
[all...]
/linux/drivers/net/wireless/broadcom/b43/
H A Dpio.h72 u16 mmio_base; member
101 u16 mmio_base; member
111 return b43_read16(q->dev, q->mmio_base + offset); in b43_piotx_read16()
116 return b43_read32(q->dev, q->mmio_base + offset); in b43_piotx_read32()
122 b43_write16(q->dev, q->mmio_base + offset, value); in b43_piotx_write16()
128 b43_write32(q->dev, q->mmio_base + offset, value); in b43_piotx_write32()
134 return b43_read16(q->dev, q->mmio_base + offset); in b43_piorx_read16()
139 return b43_read32(q->dev, q->mmio_base + offset); in b43_piorx_read32()
145 b43_write16(q->dev, q->mmio_base + offset, value); in b43_piorx_write16()
151 b43_write32(q->dev, q->mmio_base + offset, value); in b43_piorx_write32()
/linux/drivers/clk/mmp/
H A Dclk-audio.c61 void __iomem *mmio_base; member
125 aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0); in audio_pll_recalc_rate()
133 aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1); in audio_pll_recalc_rate()
218 writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL0); in audio_pll_set_rate()
222 writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL1); in audio_pll_set_rate()
259 priv->sspa_mux.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
269 priv->sysclk_div.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
282 priv->sysclk_gate.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
290 priv->sspa0_div.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
303 priv->sspa0_gate.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
[all …]
/linux/drivers/gpu/drm/xe/
H A Dxe_hw_engine.c53 u32 mmio_base; member
63 .mmio_base = RENDER_RING_BASE,
71 .mmio_base = BLT_RING_BASE,
79 .mmio_base = XEHPC_BCS1_RING_BASE,
87 .mmio_base = XEHPC_BCS2_RING_BASE,
95 .mmio_base = XEHPC_BCS3_RING_BASE,
103 .mmio_base = XEHPC_BCS4_RING_BASE,
111 .mmio_base = XEHPC_BCS5_RING_BASE,
119 .mmio_base = XEHPC_BCS6_RING_BASE,
127 .mmio_base
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/linux/drivers/thermal/
H A Dthermal_mmio.c12 void __iomem *mmio_base; member
13 u32 (*read_mmio)(void __iomem *mmio_base);
18 static u32 thermal_mmio_readb(void __iomem *mmio_base) in thermal_mmio_readb() argument
20 return readb(mmio_base); in thermal_mmio_readb()
28 t = sensor->read_mmio(sensor->mmio_base) & sensor->mask; in thermal_mmio_get_temperature()
53 sensor->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); in thermal_mmio_probe()
54 if (IS_ERR(sensor->mmio_base)) in thermal_mmio_probe()
55 return PTR_ERR(sensor->mmio_base); in thermal_mmio_probe()
/linux/drivers/pwm/
H A Dpwm-imx1.c30 void __iomem *mmio_base; member
87 max = readl(imx->mmio_base + MX1_PWMP); in pwm_imx1_config()
90 writel(max - p, imx->mmio_base + MX1_PWMS); in pwm_imx1_config()
105 value = readl(imx->mmio_base + MX1_PWMC); in pwm_imx1_enable()
107 writel(value, imx->mmio_base + MX1_PWMC); in pwm_imx1_enable()
117 value = readl(imx->mmio_base + MX1_PWMC); in pwm_imx1_disable()
119 writel(value, imx->mmio_base + MX1_PWMC); in pwm_imx1_disable()
181 imx->mmio_base = devm_platform_ioremap_resource(pdev, 0); in pwm_imx1_probe()
182 if (IS_ERR(imx->mmio_base)) in pwm_imx1_probe()
183 return PTR_ERR(imx->mmio_base); in pwm_imx1_probe()
H A Dpwm-pxa.c56 void __iomem *mmio_base; member
96 writel(prescale | PWMCR_SD, pc->mmio_base + offset + PWMCR); in pxa_pwm_config()
97 writel(dc, pc->mmio_base + offset + PWMDCR); in pxa_pwm_config()
98 writel(pv, pc->mmio_base + offset + PWMPCR); in pxa_pwm_config()
199 pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); in pwm_probe()
200 if (IS_ERR(pc->mmio_base)) in pwm_probe()
201 return PTR_ERR(pc->mmio_base); in pwm_probe()
H A Dpwm-spear.c53 void __iomem *mmio_base; member
65 return readl_relaxed(chip->mmio_base + (num << 4) + offset); in spear_pwm_readl()
72 writel_relaxed(val, chip->mmio_base + (num << 4) + offset); in spear_pwm_writel()
205 pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); in spear_pwm_probe()
206 if (IS_ERR(pc->mmio_base)) in spear_pwm_probe()
207 return PTR_ERR(pc->mmio_base); in spear_pwm_probe()
226 val = readl_relaxed(pc->mmio_base + PWMMCR); in spear_pwm_probe()
228 writel_relaxed(val, pc->mmio_base + PWMMCR); in spear_pwm_probe()
/linux/arch/x86/kernel/cpu/microcode/
H A Dintel.c96 * @mmio_base: MMIO base address for staging
103 void __iomem *mmio_base;
390 static inline u32 read_mbox_dword(void __iomem *mmio_base) in read_mbox_dword()
392 u32 dword = readl(mmio_base + MBOX_RDDATA_OFFSET); in read_mbox_dword()
395 writel(0, mmio_base + MBOX_RDDATA_OFFSET); in read_mbox_dword()
399 static inline void write_mbox_dword(void __iomem *mmio_base, u32 dword) in write_mbox_dword()
401 writel(dword, mmio_base + MBOX_WRDATA_OFFSET); in write_mbox_dword()
404 static inline u64 read_mbox_header(void __iomem *mmio_base) in read_mbox_header()
408 low = read_mbox_dword(mmio_base); in read_mbox_header()
409 high = read_mbox_dword(mmio_base); in read_mbox_header()
102 void __iomem *mmio_base; global() member
389 read_mbox_dword(void __iomem * mmio_base) read_mbox_dword() argument
398 write_mbox_dword(void __iomem * mmio_base,u32 dword) write_mbox_dword() argument
403 read_mbox_header(void __iomem * mmio_base) read_mbox_header() argument
413 write_mbox_header(void __iomem * mmio_base,u64 value) write_mbox_header() argument
419 write_mbox_data(void __iomem * mmio_base,u32 * chunk,unsigned int chunk_bytes) write_mbox_data() argument
[all...]
/linux/drivers/rtc/
H A Drtc-ep93xx.c30 void __iomem *mmio_base; member
39 comp = readl(ep93xx_rtc->mmio_base + EP93XX_RTC_SWCOMP); in ep93xx_rtc_get_swcomp()
57 time = readl(ep93xx_rtc->mmio_base + EP93XX_RTC_DATA); in ep93xx_rtc_read_time()
68 writel(secs + 1, ep93xx_rtc->mmio_base + EP93XX_RTC_LOAD); in ep93xx_rtc_set_time()
132 ep93xx_rtc->mmio_base = devm_platform_ioremap_resource(pdev, 0); in ep93xx_rtc_probe()
133 if (IS_ERR(ep93xx_rtc->mmio_base)) in ep93xx_rtc_probe()
134 return PTR_ERR(ep93xx_rtc->mmio_base); in ep93xx_rtc_probe()
/linux/drivers/video/fbdev/mb862xx/
H A Dmb862xxfbdrv.c624 par->host = par->mmio_base; in mb862xx_gdc_init()
625 par->i2c = par->mmio_base + MB862XX_I2C_BASE; in mb862xx_gdc_init()
626 par->disp = par->mmio_base + MB862XX_DISP_BASE; in mb862xx_gdc_init()
627 par->cap = par->mmio_base + MB862XX_CAP_BASE; in mb862xx_gdc_init()
628 par->draw = par->mmio_base + MB862XX_DRAW_BASE; in mb862xx_gdc_init()
629 par->geo = par->mmio_base + MB862XX_GEO_BASE; in mb862xx_gdc_init()
630 par->pio = par->mmio_base + MB862XX_PIO_BASE; in mb862xx_gdc_init()
725 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len); in of_platform_mb862xx_probe()
726 if (par->mmio_base == NULL) { in of_platform_mb862xx_probe()
772 iounmap(par->mmio_base); in of_platform_mb862xx_probe()
[all …]
/linux/drivers/thermal/intel/int340x_thermal/
H A Dprocessor_thermal_mbox.c29 data = readl(proc_priv->mmio_base + MBOX_OFFSET_INTERFACE); in wait_for_mbox_ready()
52 writel(data, (proc_priv->mmio_base + MBOX_OFFSET_DATA)); in send_mbox_write_cmd()
55 writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE)); in send_mbox_write_cmd()
73 writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE)); in send_mbox_read_cmd()
80 *resp = readl(proc_priv->mmio_base + MBOX_OFFSET_DATA); in send_mbox_read_cmd()
82 *resp = readq(proc_priv->mmio_base + MBOX_OFFSET_DATA); in send_mbox_read_cmd()
H A Dprocessor_thermal_power_floor.c42 status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET); in proc_thermal_read_power_floor_status()
94 int_status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET); in proc_thermal_check_power_floor_intr()
117 status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET); in proc_thermal_power_floor_intr_callback()
/linux/drivers/soundwire/
H A Dintel_init.c66 link->mmio_base = res->mmio_base; in intel_link_dev_register()
68 link->registers = res->mmio_base + SDW_LINK_BASE in intel_link_dev_register()
71 link->shim = res->mmio_base + res->shim_base; in intel_link_dev_register()
72 link->alh = res->mmio_base + res->alh_base; in intel_link_dev_register()
75 link->registers = res->mmio_base + SDW_IP_BASE(link_id); in intel_link_dev_register()
77 link->shim = res->mmio_base + SDW_SHIM2_GENERIC_BASE(link_id); in intel_link_dev_register()
78 link->shim_vs = res->mmio_base + SDW_SHIM2_VS_BASE(link_id); in intel_link_dev_register()
207 ctx->mmio_base = res->mmio_base; in sdw_intel_probe_controller()
/linux/drivers/platform/mellanox/
H A Dmlxbf-pmc.c124 void __iomem *mmio_base; member
1255 return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + in mlxbf_pmc_config_l3_counters()
1274 pmcaddr = pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_l3_counter()
1279 pmcaddr = pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_l3_counter()
1331 addr = pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_crspace_counter()
1353 addr = pmc->block[blk_num].mmio_base + in mlxbf_pmc_clear_crspace_counter()
1390 if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_counter()
1404 if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_counter()
1415 if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_counter()
1430 status = mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + in mlxbf_pmc_read_l3_counter()
[all …]
/linux/drivers/video/fbdev/
H A Dasiliantfb.c49 #define mmio_base (p->screen_base + 0x400000) macro
52 writeb((num), mmio_base + (ap)); writeb((val), mmio_base + (dp)); \
87 readb(mmio_base + 0x7b4); in mm_write_ar()
218 writeb(0xc7, mmio_base + 0x784); /* set misc output reg */ in asiliant_set_timing()
220 writeb(0x07, mmio_base + 0x784); /* set misc output reg */ in asiliant_set_timing()
318 writeb(regno, mmio_base + 0x790); in asiliantfb_setcolreg()
320 writeb(red, mmio_base + 0x791); in asiliantfb_setcolreg()
321 writeb(green, mmio_base + 0x791); in asiliantfb_setcolreg()
322 writeb(blue, mmio_base + 0x791); in asiliantfb_setcolreg()
472 writeb(0x20, mmio_base + 0x780); in chips_hw_init()
[all …]
H A Dpvr2fb.c82 #define DISP_BASE par->mmio_base
144 void __iomem *mmio_base; /* MMIO base */ member
234 fb_writel(type, par->mmio_base + 0x108); in pvr2fb_set_pal_type()
241 fb_writel(val, par->mmio_base + 0x1000 + (4 * regno)); in pvr2fb_set_pal_entry()
799 par->mmio_base = ioremap(pvr2_fix.mmio_start, in pvr2fb_common_init()
801 if (!par->mmio_base) { in pvr2fb_common_init()
838 rev = fb_readl(par->mmio_base + 0x04); in pvr2fb_common_init()
866 if (par->mmio_base) in pvr2fb_common_init()
867 iounmap(par->mmio_base); in pvr2fb_common_init()
933 if (currentpar->mmio_base) { in pvr2fb_dc_exit()
[all...]
/linux/drivers/acpi/x86/
H A Dlpss.c97 void __iomem *mmio_base; member
135 val = readl(pdata->mmio_base + offset); in lpss_uart_setup()
136 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); in lpss_uart_setup()
138 val = readl(pdata->mmio_base + LPSS_UART_CPR); in lpss_uart_setup()
141 val = readl(pdata->mmio_base + offset); in lpss_uart_setup()
143 writel(val, pdata->mmio_base + offset); in lpss_uart_setup()
153 val = readl(pdata->mmio_base + offset); in lpss_deassert_reset()
155 writel(val, pdata->mmio_base + offset); in lpss_deassert_reset()
194 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) in byt_i2c_setup()
197 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); in byt_i2c_setup()
[all …]
/linux/drivers/iommu/amd/
H A Dppr.c40 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, in amd_iommu_enable_ppr_log()
44 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); in amd_iommu_enable_ppr_log()
45 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); in amd_iommu_enable_ppr_log()
171 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); in amd_iommu_poll_ppr_log()
172 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); in amd_iommu_poll_ppr_log()
207 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); in amd_iommu_poll_ppr_log()
/linux/drivers/input/keyboard/
H A Dep93xx_keypad.c67 void __iomem *mmio_base; member
86 status = __raw_readl(keypad->mmio_base + KEY_REG); in ep93xx_keypad_irq_handler()
138 __raw_writel(val, keypad->mmio_base + KEY_INIT); in ep93xx_keypad_config()
218 keypad->mmio_base = devm_platform_ioremap_resource(pdev, 0); in ep93xx_keypad_probe()
219 if (IS_ERR(keypad->mmio_base)) in ep93xx_keypad_probe()
220 return PTR_ERR(keypad->mmio_base); in ep93xx_keypad_probe()

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