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Searched refs:mmio_base (Results 1 – 25 of 77) sorted by relevance

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/linux/drivers/edac/
H A Dal_mc_edac.c57 void __iomem *mmio_base; member
83 eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT); in handle_ce()
88 ecccaddr0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR0); in handle_ce()
89 ecccaddr1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR1); in handle_ce()
90 ecccsyn0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND0); in handle_ce()
91 ecccsyn1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND1); in handle_ce()
92 ecccsyn2 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND2); in handle_ce()
95 al_mc->mmio_base + AL_MC_ECC_CLEAR); in handle_ce()
128 eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT); in handle_ue()
133 eccuaddr0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_ADDR0); in handle_ue()
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dpio.h72 u16 mmio_base; member
101 u16 mmio_base; member
111 return b43_read16(q->dev, q->mmio_base + offset); in b43_piotx_read16()
116 return b43_read32(q->dev, q->mmio_base + offset); in b43_piotx_read32()
122 b43_write16(q->dev, q->mmio_base + offset, value); in b43_piotx_write16()
128 b43_write32(q->dev, q->mmio_base + offset, value); in b43_piotx_write32()
134 return b43_read16(q->dev, q->mmio_base + offset); in b43_piorx_read16()
139 return b43_read32(q->dev, q->mmio_base + offset); in b43_piorx_read32()
145 b43_write16(q->dev, q->mmio_base + offset, value); in b43_piorx_write16()
151 b43_write32(q->dev, q->mmio_base + offset, value); in b43_piorx_write32()
H A Dpio.c135 q->mmio_base = index_to_pioqueue_base(dev, index) + in b43_setup_pioqueue_tx()
169 q->mmio_base = index_to_pioqueue_base(dev, index) + in b43_setup_pioqueue_rx()
330 q->mmio_base + B43_PIO_TXDATA, in tx_write_2byte_queue()
342 q->mmio_base + B43_PIO_TXDATA, in tx_write_2byte_queue()
384 q->mmio_base + B43_PIO8_TXDATA, in tx_write_4byte_queue()
412 q->mmio_base + B43_PIO8_TXDATA, in tx_write_4byte_queue()
658 q->mmio_base + B43_PIO8_RXDATA, in pio_rx_frame()
662 q->mmio_base + B43_PIO_RXDATA, in pio_rx_frame()
706 q->mmio_base + B43_PIO8_RXDATA, in pio_rx_frame()
714 q->mmio_base + B43_PIO8_RXDATA, in pio_rx_frame()
[all …]
/linux/drivers/clk/mmp/
H A Dclk-audio.c61 void __iomem *mmio_base; member
125 aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0); in audio_pll_recalc_rate()
133 aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1); in audio_pll_recalc_rate()
218 writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL0); in audio_pll_set_rate()
222 writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL1); in audio_pll_set_rate()
259 priv->sspa_mux.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
269 priv->sysclk_div.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
282 priv->sysclk_gate.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
290 priv->sspa0_div.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
303 priv->sspa0_gate.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
[all …]
/linux/drivers/thermal/
H A Dthermal_mmio.c12 void __iomem *mmio_base; member
13 u32 (*read_mmio)(void __iomem *mmio_base);
18 static u32 thermal_mmio_readb(void __iomem *mmio_base) in thermal_mmio_readb() argument
20 return readb(mmio_base); in thermal_mmio_readb()
28 t = sensor->read_mmio(sensor->mmio_base) & sensor->mask; in thermal_mmio_get_temperature()
53 sensor->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); in thermal_mmio_probe()
54 if (IS_ERR(sensor->mmio_base)) in thermal_mmio_probe()
55 return PTR_ERR(sensor->mmio_base); in thermal_mmio_probe()
/linux/drivers/gpu/drm/xe/
H A Dxe_hw_engine.c53 u32 mmio_base; member
63 .mmio_base = RENDER_RING_BASE,
71 .mmio_base = BLT_RING_BASE,
79 .mmio_base = XEHPC_BCS1_RING_BASE,
87 .mmio_base = XEHPC_BCS2_RING_BASE,
95 .mmio_base = XEHPC_BCS3_RING_BASE,
103 .mmio_base = XEHPC_BCS4_RING_BASE,
111 .mmio_base = XEHPC_BCS5_RING_BASE,
119 .mmio_base = XEHPC_BCS6_RING_BASE,
127 .mmio_base = XEHPC_BCS7_RING_BASE,
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H A Dxe_rtp.c231 u32 mmio_base, in rtp_add_sr_entry() argument
245 sr_entry.reg.addr += mmio_base; in rtp_add_sr_entry()
255 u32 mmio_base; in rtp_process_one_sr() local
264 mmio_base = hwe->mmio_base; in rtp_process_one_sr()
266 mmio_base = 0; in rtp_process_one_sr()
268 rtp_add_sr_entry(action, gt, hwe, mmio_base, sr); in rtp_process_one_sr()
/linux/drivers/rtc/
H A Drtc-ep93xx.c29 void __iomem *mmio_base; member
38 comp = readl(ep93xx_rtc->mmio_base + EP93XX_RTC_SWCOMP); in ep93xx_rtc_get_swcomp()
56 time = readl(ep93xx_rtc->mmio_base + EP93XX_RTC_DATA); in ep93xx_rtc_read_time()
67 writel(secs + 1, ep93xx_rtc->mmio_base + EP93XX_RTC_LOAD); in ep93xx_rtc_set_time()
131 ep93xx_rtc->mmio_base = devm_platform_ioremap_resource(pdev, 0); in ep93xx_rtc_probe()
132 if (IS_ERR(ep93xx_rtc->mmio_base)) in ep93xx_rtc_probe()
133 return PTR_ERR(ep93xx_rtc->mmio_base); in ep93xx_rtc_probe()
/linux/drivers/thermal/intel/int340x_thermal/
H A Dprocessor_thermal_mbox.c29 data = readl(proc_priv->mmio_base + MBOX_OFFSET_INTERFACE); in wait_for_mbox_ready()
52 writel(data, (proc_priv->mmio_base + MBOX_OFFSET_DATA)); in send_mbox_write_cmd()
55 writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE)); in send_mbox_write_cmd()
73 writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE)); in send_mbox_read_cmd()
80 *resp = readl(proc_priv->mmio_base + MBOX_OFFSET_DATA); in send_mbox_read_cmd()
82 *resp = readq(proc_priv->mmio_base + MBOX_OFFSET_DATA); in send_mbox_read_cmd()
H A Dprocessor_thermal_power_floor.c42 status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET); in proc_thermal_read_power_floor_status()
94 int_status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET); in proc_thermal_check_power_floor_intr()
117 status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET); in proc_thermal_power_floor_intr_callback()
/linux/drivers/pwm/
H A Dpwm-spear.c53 void __iomem *mmio_base; member
65 return readl_relaxed(chip->mmio_base + (num << 4) + offset); in spear_pwm_readl()
72 writel_relaxed(val, chip->mmio_base + (num << 4) + offset); in spear_pwm_writel()
205 pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); in spear_pwm_probe()
206 if (IS_ERR(pc->mmio_base)) in spear_pwm_probe()
207 return PTR_ERR(pc->mmio_base); in spear_pwm_probe()
226 val = readl_relaxed(pc->mmio_base + PWMMCR); in spear_pwm_probe()
228 writel_relaxed(val, pc->mmio_base + PWMMCR); in spear_pwm_probe()
H A Dpwm-pxa.c55 void __iomem *mmio_base; member
95 writel(prescale | PWMCR_SD, pc->mmio_base + offset + PWMCR); in pxa_pwm_config()
96 writel(dc, pc->mmio_base + offset + PWMDCR); in pxa_pwm_config()
97 writel(pv, pc->mmio_base + offset + PWMPCR); in pxa_pwm_config()
192 pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); in pwm_probe()
193 if (IS_ERR(pc->mmio_base)) in pwm_probe()
194 return PTR_ERR(pc->mmio_base); in pwm_probe()
/linux/drivers/ata/
H A Dpata_sil680.c340 void __iomem *mmio_base; in sil680_init_one() local
380 mmio_base = host->iomap[SIL680_MMIO_BAR]; in sil680_init_one()
381 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00; in sil680_init_one()
382 host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80; in sil680_init_one()
383 host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a; in sil680_init_one()
384 host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a; in sil680_init_one()
386 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08; in sil680_init_one()
387 host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0; in sil680_init_one()
388 host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca; in sil680_init_one()
389 host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca; in sil680_init_one()
/linux/drivers/soundwire/
H A Dintel_init.c66 link->mmio_base = res->mmio_base; in intel_link_dev_register()
68 link->registers = res->mmio_base + SDW_LINK_BASE in intel_link_dev_register()
71 link->shim = res->mmio_base + res->shim_base; in intel_link_dev_register()
72 link->alh = res->mmio_base + res->alh_base; in intel_link_dev_register()
75 link->registers = res->mmio_base + SDW_IP_BASE(link_id); in intel_link_dev_register()
77 link->shim = res->mmio_base + SDW_SHIM2_GENERIC_BASE(link_id); in intel_link_dev_register()
78 link->shim_vs = res->mmio_base + SDW_SHIM2_VS_BASE(link_id); in intel_link_dev_register()
207 ctx->mmio_base = res->mmio_base; in sdw_intel_probe_controller()
/linux/drivers/platform/mellanox/
H A Dmlxbf-pmc.c124 void __iomem *mmio_base; member
1255 return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + in mlxbf_pmc_config_l3_counters()
1274 pmcaddr = pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_l3_counter()
1279 pmcaddr = pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_l3_counter()
1331 addr = pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_crspace_counter()
1353 addr = pmc->block[blk_num].mmio_base + in mlxbf_pmc_clear_crspace_counter()
1390 if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_counter()
1404 if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_counter()
1415 if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_counter()
1430 status = mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + in mlxbf_pmc_read_l3_counter()
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/linux/drivers/video/fbdev/
H A Dasiliantfb.c49 #define mmio_base (p->screen_base + 0x400000) macro
52 writeb((num), mmio_base + (ap)); writeb((val), mmio_base + (dp)); \
87 readb(mmio_base + 0x7b4); in mm_write_ar()
218 writeb(0xc7, mmio_base + 0x784); /* set misc output reg */ in asiliant_set_timing()
220 writeb(0x07, mmio_base + 0x784); /* set misc output reg */ in asiliant_set_timing()
318 writeb(regno, mmio_base + 0x790); in asiliantfb_setcolreg()
320 writeb(red, mmio_base + 0x791); in asiliantfb_setcolreg()
321 writeb(green, mmio_base + 0x791); in asiliantfb_setcolreg()
322 writeb(blue, mmio_base + 0x791); in asiliantfb_setcolreg()
472 writeb(0x20, mmio_base + 0x780); in chips_hw_init()
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/linux/drivers/acpi/x86/
H A Dlpss.c97 void __iomem *mmio_base; member
135 val = readl(pdata->mmio_base + offset); in lpss_uart_setup()
136 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); in lpss_uart_setup()
138 val = readl(pdata->mmio_base + LPSS_UART_CPR); in lpss_uart_setup()
141 val = readl(pdata->mmio_base + offset); in lpss_uart_setup()
143 writel(val, pdata->mmio_base + offset); in lpss_uart_setup()
153 val = readl(pdata->mmio_base + offset); in lpss_deassert_reset()
155 writel(val, pdata->mmio_base + offset); in lpss_deassert_reset()
194 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) in byt_i2c_setup()
197 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); in byt_i2c_setup()
[all …]
/linux/drivers/input/keyboard/
H A Dep93xx_keypad.c66 void __iomem *mmio_base; member
85 status = __raw_readl(keypad->mmio_base + KEY_REG); in ep93xx_keypad_irq_handler()
137 __raw_writel(val, keypad->mmio_base + KEY_INIT); in ep93xx_keypad_config()
217 keypad->mmio_base = devm_platform_ioremap_resource(pdev, 0); in ep93xx_keypad_probe()
218 if (IS_ERR(keypad->mmio_base)) in ep93xx_keypad_probe()
219 return PTR_ERR(keypad->mmio_base); in ep93xx_keypad_probe()
/linux/drivers/thermal/st/
H A Dst_thermal_memmap.c121 sensor->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); in st_mmap_regmap_init()
122 if (IS_ERR(sensor->mmio_base)) in st_mmap_regmap_init()
123 return PTR_ERR(sensor->mmio_base); in st_mmap_regmap_init()
125 sensor->regmap = devm_regmap_init_mmio(dev, sensor->mmio_base, in st_mmap_regmap_init()
/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dpio.h53 u16 mmio_base; member
87 return b43legacy_read16(queue->dev, queue->mmio_base + offset); in b43legacy_pio_read()
94 b43legacy_write16(queue->dev, queue->mmio_base + offset, value); in b43legacy_pio_write()
H A Ddma.h145 u16 mmio_base; member
171 return b43legacy_read32(ring->dev, ring->mmio_base + offset); in b43legacy_dma_read()
178 b43legacy_write32(ring->dev, ring->mmio_base + offset, value); in b43legacy_dma_write()
/linux/drivers/video/fbdev/aty/
H A Dradeonfb.h299 void __iomem *mmio_base; member
376 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
377 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
378 #define INREG16(addr) readw((rinfo->mmio_base)+addr)
379 #define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
380 #define INREG(addr) readl((rinfo->mmio_base)+addr)
381 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
/linux/drivers/iommu/amd/
H A Dinit.c252 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in init_translation_status()
373 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_cwwb_range()
380 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_cwwb_range()
391 BUG_ON(iommu->mmio_base == NULL); in iommu_set_device_table()
398 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, in iommu_set_device_table()
406 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_set()
410 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_set()
432 if (!iommu->mmio_base) in iommu_disable()
475 if (iommu->mmio_base) in iommu_unmap_mmio_space()
476 iounmap(iommu->mmio_base); in iommu_unmap_mmio_space()
[all …]
/linux/drivers/scsi/
H A Dstex.c314 void __iomem *mmio_base; /* iomapped PCI memory space */ member
525 writel(hba->req_head, hba->mmio_base + IMR0); in stex_send_cmd()
526 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL); in stex_send_cmd()
527 readl(hba->mmio_base + IDBL); /* flush */ in stex_send_cmd()
555 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI); in stex_ss_send_cmd()
556 writel(addr, hba->mmio_base + YH2I_REQ); in stex_ss_send_cmd()
558 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI); in stex_ss_send_cmd()
559 readl(hba->mmio_base + YH2I_REQ_HI); /* flush */ in stex_ss_send_cmd()
560 writel(addr, hba->mmio_base + YH2I_REQ); in stex_ss_send_cmd()
561 readl(hba->mmio_base + YH2I_REQ); /* flush */ in stex_ss_send_cmd()
[all …]
/linux/sound/soc/xilinx/
H A Dxlnx_formatter_pcm.c245 static int xlnx_formatter_pcm_reset(void __iomem *mmio_base) in xlnx_parse_aes_params()
249 val = readl(mmio_base + XLNX_AUD_CTRL); in xlnx_formatter_pcm_reset()
251 writel(val, mmio_base + XLNX_AUD_CTRL); in xlnx_formatter_pcm_reset()
253 val = readl(mmio_base + XLNX_AUD_CTRL); in xlnx_formatter_pcm_reset()
258 val = readl(mmio_base + XLNX_AUD_CTRL); in xlnx_formatter_pcm_reset()
266 static void xlnx_formatter_disable_irqs(void __iomem *mmio_base, int stream) in xlnx_formatter_pcm_reset()
270 val = readl(mmio_base + XLNX_AUD_CTRL); in xlnx_formatter_disable_irqs()
275 writel(val, mmio_base + XLNX_AUD_CTRL); in xlnx_formatter_disable_irqs()
247 xlnx_formatter_pcm_reset(void __iomem * mmio_base) xlnx_formatter_pcm_reset() argument
268 xlnx_formatter_disable_irqs(void __iomem * mmio_base,int stream) xlnx_formatter_disable_irqs() argument

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