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Searched refs:mmio (Results 1 – 25 of 464) sorted by relevance

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/linux/sound/pci/au88x0/
H A Dau88x0_xtalk.c248 hwwrite(vortex->mmio, 0x24200 + i * 0x24, coefs[i][0]); in vortex_XtalkHw_SetLeftEQ()
249 hwwrite(vortex->mmio, 0x24204 + i * 0x24, coefs[i][1]); in vortex_XtalkHw_SetLeftEQ()
250 hwwrite(vortex->mmio, 0x24208 + i * 0x24, coefs[i][2]); in vortex_XtalkHw_SetLeftEQ()
251 hwwrite(vortex->mmio, 0x2420c + i * 0x24, coefs[i][3]); in vortex_XtalkHw_SetLeftEQ()
252 hwwrite(vortex->mmio, 0x24210 + i * 0x24, coefs[i][4]); in vortex_XtalkHw_SetLeftEQ()
254 hwwrite(vortex->mmio, 0x24538, arg_0 & 0xffff); in vortex_XtalkHw_SetLeftEQ()
255 hwwrite(vortex->mmio, 0x2453C, arg_4 & 0xffff); in vortex_XtalkHw_SetLeftEQ()
265 hwwrite(vortex->mmio, 0x242b4 + i * 0x24, coefs[i][0]); in vortex_XtalkHw_SetRightEQ()
266 hwwrite(vortex->mmio, 0x242b8 + i * 0x24, coefs[i][1]); in vortex_XtalkHw_SetRightEQ()
267 hwwrite(vortex->mmio, 0x242bc + i * 0x24, coefs[i][2]); in vortex_XtalkHw_SetRightEQ()
[all …]
H A Dau88x0_core.c79 hwwrite(vortex->mmio, VORTEX_MIXER_SR, in vortex_mixer_en_sr()
80 hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel)); in vortex_mixer_en_sr()
84 hwwrite(vortex->mmio, VORTEX_MIXER_SR, in vortex_mixer_dis_sr()
85 hwread(vortex->mmio, VORTEX_MIXER_SR) & ~(0x1 << channel)); in vortex_mixer_dis_sr()
93 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + ((mix << 5) + channel),
95 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + ((mix << 5) + channel),
102 a = hwread(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2)) & 0xff;
114 a = hwread(vortex->mmio,
139 a = hwread(vortex->mmio,
143 hwwrite(vortex->mmio,
[all …]
H A Dau88x0_synth.c33 temp = hwread(vortex->mmio, WT_STEREO(wt)); in vortex_wt_setstereo()
36 hwwrite(vortex->mmio, WT_STEREO(wt), temp); in vortex_wt_setstereo()
45 temp = hwread(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0)); in vortex_wt_setdsout()
50 hwwrite(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0), temp); in vortex_wt_setdsout()
70 hwwrite(vortex->mmio, WT_SRAMP(0), 0x880000); in vortex_wt_allocroute()
73 hwwrite(vortex->mmio, WT_SRAMP(1), 0x880000); in vortex_wt_allocroute()
76 hwwrite(vortex->mmio, WT_PARM(wt, 0), 0); in vortex_wt_allocroute()
77 hwwrite(vortex->mmio, WT_PARM(wt, 1), 0); in vortex_wt_allocroute()
78 hwwrite(vortex->mmio, WT_PARM(wt, 2), 0); in vortex_wt_allocroute()
80 temp = hwread(vortex->mmio, WT_PARM(wt, 3)); in vortex_wt_allocroute()
[all …]
H A Dau88x0_eq.c41 hwwrite(vortex->mmio, 0x2b3c4, gain); in vortex_EqHw_SetTimeConsts()
42 hwwrite(vortex->mmio, 0x2b3c8, level); in vortex_EqHw_SetTimeConsts()
60 hwwrite(vortex->mmio, 0x2b000 + n * 0x30, coefs[i + 0]); in vortex_EqHw_SetLeftCoefs()
61 hwwrite(vortex->mmio, 0x2b004 + n * 0x30, coefs[i + 1]); in vortex_EqHw_SetLeftCoefs()
64 hwwrite(vortex->mmio, 0x2b008 + n * 0x30, coefs[i + 2]); in vortex_EqHw_SetLeftCoefs()
65 hwwrite(vortex->mmio, 0x2b00c + n * 0x30, coefs[i + 3]); in vortex_EqHw_SetLeftCoefs()
66 hwwrite(vortex->mmio, 0x2b010 + n * 0x30, coefs[i + 4]); in vortex_EqHw_SetLeftCoefs()
68 hwwrite(vortex->mmio, 0x2b008 + n * 0x30, sign_invert(coefs[2 + i])); in vortex_EqHw_SetLeftCoefs()
69 hwwrite(vortex->mmio, 0x2b00c + n * 0x30, sign_invert(coefs[3 + i])); in vortex_EqHw_SetLeftCoefs()
70 hwwrite(vortex->mmio, in vortex_EqHw_SetLeftCoefs()
[all...]
H A Dau88x0_mpu401.c42 (hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) | in snd_vortex_midi()
44 hwwrite(vortex->mmio, VORTEX_CTRL, temp); in snd_vortex_midi()
48 (hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) & in snd_vortex_midi()
50 hwwrite(vortex->mmio, VORTEX_CTRL, temp); in snd_vortex_midi()
54 temp = hwread(vortex->mmio, VORTEX_CTRL2) & 0xffff00cf; in snd_vortex_midi()
56 hwwrite(vortex->mmio, VORTEX_CTRL2, temp); in snd_vortex_midi()
57 hwwrite(vortex->mmio, VORTEX_MIDI_CMD, MPU401_RESET); in snd_vortex_midi()
60 temp = hwread(vortex->mmio, VORTEX_MIDI_DATA); in snd_vortex_midi()
66 hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, in snd_vortex_midi()
67 hwread(vortex->mmio, VORTEX_IRQ_CTRL) | IRQ_MIDI); in snd_vortex_midi()
[all …]
H A Dau88x0_a3d.c25 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
27 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
29 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
31 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
51 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
54 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
57 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
66 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
69 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
72 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
[all …]
/linux/drivers/video/fbdev/i810/
H A Di810_main.c168 static void i810_screen_off(u8 __iomem *mmio, u8 mode) in i810_screen_off() argument
173 i810_writeb(SR_INDEX, mmio, SR01); in i810_screen_off()
174 val = i810_readb(SR_DATA, mmio); in i810_screen_off()
178 while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--); in i810_screen_off()
179 i810_writeb(SR_INDEX, mmio, SR01); in i810_screen_off()
180 i810_writeb(SR_DATA, mmio, val); in i810_screen_off()
192 static void i810_dram_off(u8 __iomem *mmio, u8 mode) in i810_dram_off() argument
196 val = i810_readb(DRAMCH, mmio); in i810_dram_off()
199 i810_writeb(DRAMCH, mmio, val); in i810_dram_off()
211 static void i810_protect_regs(u8 __iomem *mmio, int mode) in i810_protect_regs() argument
[all …]
H A Di810_accel.c36 static inline void i810_report_error(u8 __iomem *mmio) in i810_report_error() argument
43 i810_readw(IIR, mmio), in i810_report_error()
44 i810_readb(EIR, mmio), in i810_report_error()
45 i810_readl(PGTBL_ER, mmio), in i810_report_error()
46 i810_readl(IPEIR, mmio), in i810_report_error()
47 i810_readl(IPEHR, mmio)); in i810_report_error()
63 u8 __iomem *mmio = par->mmio_start_virtual; in wait_for_space() local
67 head = i810_readl(IRING + 4, mmio) & RBUFFER_HEAD_MASK; in wait_for_space()
76 i810_report_error(mmio); in wait_for_space()
93 u8 __iomem *mmio = par->mmio_start_virtual; in wait_for_engine_idle() local
[all …]
H A Di810-i2c.c46 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_setscl() local
49 i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK | SCL_VAL_MASK); in i810i2c_setscl()
51 i810_writel(mmio, chan->ddc_base, SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK); in i810i2c_setscl()
52 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setscl()
59 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_setsda() local
62 i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK | SDA_VAL_MASK); in i810i2c_setsda()
64 i810_writel(mmio, chan->ddc_base, SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK); in i810i2c_setsda()
65 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setsda()
72 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_getscl() local
74 i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK); in i810i2c_getscl()
[all …]
/linux/drivers/net/ethernet/amd/
H A Damd8111e.c101 void __iomem *mmio = lp->mmio; in amd8111e_read_phy() local
105 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
107 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
110 ((reg & 0x1f) << 16), mmio + PHY_ACCESS); in amd8111e_read_phy()
112 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
131 void __iomem *mmio = lp->mmio; in amd8111e_write_phy() local
134 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
136 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
139 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS); in amd8111e_write_phy()
142 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
[all …]
/linux/drivers/phy/mediatek/
H A Dphy-mtk-ufs.c41 void __iomem *mmio; member
62 void __iomem *mmio = phy->mmio; in ufs_mtk_phy_set_active() local
65 mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_PWR_ON); in ufs_mtk_phy_set_active()
66 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON); in ufs_mtk_phy_set_active()
69 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN); in ufs_mtk_phy_set_active()
70 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN); in ufs_mtk_phy_set_active()
73 mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_PWR_ON); in ufs_mtk_phy_set_active()
74 mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON); in ufs_mtk_phy_set_active()
77 mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_ISO_EN); in ufs_mtk_phy_set_active()
78 mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN); in ufs_mtk_phy_set_active()
[all …]
/linux/drivers/comedi/drivers/
H A Dni_pcidio.c311 dev->mmio + DMA_LINE_CONTROL_GROUP1); in ni_pcidio_request_di_mite_channel()
327 dev->mmio + DMA_LINE_CONTROL_GROUP1); in ni_pcidio_release_di_mite_channel()
393 status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS); in nidio_interrupt()
394 flags = readb(dev->mmio + GROUP_1_FLAGS); in nidio_interrupt()
408 dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL); in nidio_interrupt()
420 writeb(0x00, dev->mmio + in nidio_interrupt()
425 auxdata = readl(dev->mmio + GROUP_1_FIFO); in nidio_interrupt()
427 flags = readb(dev->mmio + GROUP_1_FLAGS); in nidio_interrupt()
432 writeb(CLEAR_EXPIRED, dev->mmio + GROUP_1_SECOND_CLEAR); in nidio_interrupt()
435 writeb(0x00, dev->mmio + OP_MODE); in nidio_interrupt()
[all …]
H A Drtd520.c464 writel(0, dev->mmio + LAS0_CGT_CLEAR); in rtd_load_channelgain_list()
465 writel(1, dev->mmio + LAS0_CGT_ENABLE); in rtd_load_channelgain_list()
468 dev->mmio + LAS0_CGT_WRITE); in rtd_load_channelgain_list()
471 writel(0, dev->mmio + LAS0_CGT_ENABLE); in rtd_load_channelgain_list()
473 dev->mmio + LAS0_CGL_WRITE); in rtd_load_channelgain_list()
488 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); in rtd520_probe_fifo_depth()
491 writel(0, dev->mmio + LAS0_ADC_CONVERSION); in rtd520_probe_fifo_depth()
496 writew(0, dev->mmio + LAS0_ADC); in rtd520_probe_fifo_depth()
498 fifo_status = readl(dev->mmio + LAS0_ADC); in rtd520_probe_fifo_depth()
508 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); in rtd520_probe_fifo_depth()
[all …]
H A Dni_6527.c89 writeb(val & 0xff, dev->mmio + NI6527_FILT_INTERVAL_REG(0)); in ni6527_set_filter_interval()
91 dev->mmio + NI6527_FILT_INTERVAL_REG(1)); in ni6527_set_filter_interval()
93 dev->mmio + NI6527_FILT_INTERVAL_REG(2)); in ni6527_set_filter_interval()
95 writeb(NI6527_CLR_INTERVAL, dev->mmio + NI6527_CLR_REG); in ni6527_set_filter_interval()
104 writeb(val & 0xff, dev->mmio + NI6527_FILT_ENA_REG(0)); in ni6527_set_filter_enable()
105 writeb((val >> 8) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(1)); in ni6527_set_filter_enable()
106 writeb((val >> 16) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(2)); in ni6527_set_filter_enable()
150 val = readb(dev->mmio + NI6527_DI_REG(0)); in ni6527_di_insn_bits()
151 val |= (readb(dev->mmio + NI6527_DI_REG(1)) << 8); in ni6527_di_insn_bits()
152 val |= (readb(dev->mmio + NI6527_DI_REG(2)) << 16); in ni6527_di_insn_bits()
[all …]
H A Dme_daq.c176 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_dio_insn_config()
186 void __iomem *mmio_porta = dev->mmio + ME_DIO_PORT_A_REG; in me_dio_insn_bits()
187 void __iomem *mmio_portb = dev->mmio + ME_DIO_PORT_B_REG; in me_dio_insn_bits()
221 status = readw(dev->mmio + ME_STATUS_REG); in me_ai_eoc()
251 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ai_insn_read()
253 writew(0x00, dev->mmio + ME_STATUS_REG); /* clear interrupts */ in me_ai_insn_read()
257 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ai_insn_read()
265 writew(val, dev->mmio + ME_AI_FIFO_REG); in me_ai_insn_read()
269 writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG); in me_ai_insn_read()
273 readw(dev->mmio + ME_CTRL1_REG); in me_ai_insn_read()
[all …]
H A Ddt3000.c231 writew(cmd, dev->mmio + DPR_CMD_MBX); in dt3k_send_cmd()
234 status = readw(dev->mmio + DPR_CMD_MBX); in dt3k_send_cmd()
250 writew(subsys, dev->mmio + DPR_SUBSYS); in dt3k_readsingle()
252 writew(chan, dev->mmio + DPR_PARAMS(0)); in dt3k_readsingle()
253 writew(gain, dev->mmio + DPR_PARAMS(1)); in dt3k_readsingle()
257 return readw(dev->mmio + DPR_PARAMS(2)); in dt3k_readsingle()
263 writew(subsys, dev->mmio + DPR_SUBSYS); in dt3k_writesingle()
265 writew(chan, dev->mmio + DPR_PARAMS(0)); in dt3k_writesingle()
266 writew(0, dev->mmio + DPR_PARAMS(1)); in dt3k_writesingle()
267 writew(data, dev->mmio + DPR_PARAMS(2)); in dt3k_writesingle()
[all …]
/linux/drivers/ata/
H A Dsata_sx4.c419 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; in pdc20621_dma_prep() local
428 mmio += PDC_CHIP0_OFS; in pdc20621_dma_prep()
466 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); in pdc20621_dma_prep()
478 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; in pdc20621_nodata_prep() local
484 mmio += PDC_CHIP0_OFS; in pdc20621_nodata_prep()
500 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); in pdc20621_nodata_prep()
529 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; in __pdc20621_push_hdma() local
532 mmio += PDC_CHIP0_OFS; in __pdc20621_push_hdma()
534 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); in __pdc20621_push_hdma()
535 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ in __pdc20621_push_hdma()
[all …]
H A Dahci_imx.c83 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert) in imx_phy_crbit_assert() argument
90 crval = readl(mmio + IMX_P0PHYCR); in imx_phy_crbit_assert()
95 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_crbit_assert()
99 srval = readl(mmio + IMX_P0PHYSR); in imx_phy_crbit_assert()
108 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio) in imx_phy_reg_addressing() argument
114 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_reg_addressing()
117 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true); in imx_phy_reg_addressing()
122 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false); in imx_phy_reg_addressing()
129 static int imx_phy_reg_write(u16 val, void __iomem *mmio) in imx_phy_reg_write() argument
135 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_reg_write()
[all …]
/linux/sound/soc/au1x/
H A Dpsc.h13 void __iomem *mmio; member
26 #define PSC_CTRL(x) ((x)->mmio + PSC_CTRL_OFFSET)
27 #define PSC_SEL(x) ((x)->mmio + PSC_SEL_OFFSET)
28 #define I2S_STAT(x) ((x)->mmio + PSC_I2SSTAT_OFFSET)
29 #define I2S_CFG(x) ((x)->mmio + PSC_I2SCFG_OFFSET)
30 #define I2S_PCR(x) ((x)->mmio + PSC_I2SPCR_OFFSET)
31 #define AC97_CFG(x) ((x)->mmio + PSC_AC97CFG_OFFSET)
32 #define AC97_CDC(x) ((x)->mmio + PSC_AC97CDC_OFFSET)
33 #define AC97_EVNT(x) ((x)->mmio + PSC_AC97EVNT_OFFSET)
34 #define AC97_PCR(x) ((x)->mmio + PSC_AC97PCR_OFFSET)
[all …]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-combphy.c202 void __iomem *mmio; member
221 temp = readl(priv->mmio + reg); in rockchip_combphy_updatel()
223 writel(temp, priv->mmio + reg); in rockchip_combphy_updatel()
406 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rockchip_combphy_probe()
407 if (IS_ERR(priv->mmio)) { in rockchip_combphy_probe()
408 ret = PTR_ERR(priv->mmio); in rockchip_combphy_probe()
524 writel(0x570804f0, priv->mmio + RK3528_PHYREG42); in rk3528_combphy_cfg()
629 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); in rk3562_combphy_cfg()
636 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); in rk3562_combphy_cfg()
639 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); in rk3562_combphy_cfg()
[all …]
/linux/arch/mips/kvm/
H A Demulate.c976 void *data = run->mmio.data; in kvm_mips_emulate_store()
991 run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa( in kvm_mips_emulate_store()
993 if (run->mmio.phys_addr == KVM_INVALID_ADDR) in kvm_mips_emulate_store()
999 run->mmio.len = 8; in kvm_mips_emulate_store()
1009 run->mmio.len = 4; in kvm_mips_emulate_store()
1018 run->mmio.len = 2; in kvm_mips_emulate_store()
1027 run->mmio.len = 1; in kvm_mips_emulate_store()
1036 run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa( in kvm_mips_emulate_store()
1038 run->mmio.len = 4; in kvm_mips_emulate_store()
1066 run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa( in kvm_mips_emulate_store()
[all …]
/linux/sound/soc/xilinx/
H A Dxlnx_formatter_pcm.c79 void __iomem *mmio; member
99 void __iomem *mmio; member
287 reg = adata->mmio + XLNX_MM2S_OFFSET + XLNX_AUD_STS; in xlnx_mm2s_irq_handler()
306 reg = adata->mmio + XLNX_S2MM_OFFSET + XLNX_AUD_STS; in xlnx_s2mm_irq_handler()
354 stream_data->mmio = adata->mmio + XLNX_MM2S_OFFSET; in xlnx_formatter_pcm_open()
363 stream_data->mmio = adata->mmio + XLNX_S2MM_OFFSET; in xlnx_formatter_pcm_open()
367 val = readl(adata->mmio + XLNX_AUD_CORE_CONFIG); in xlnx_formatter_pcm_open()
412 val = readl(stream_data->mmio + XLNX_AUD_CTRL); in xlnx_formatter_pcm_open()
414 writel(val, stream_data->mmio + XLNX_AUD_CTRL); in xlnx_formatter_pcm_open()
426 ret = xlnx_formatter_pcm_reset(stream_data->mmio); in xlnx_formatter_pcm_close()
[all …]
/linux/drivers/ntb/hw/intel/
H A Dntb_hw_gen3.c147 void __iomem *mmio; in gen3_setup_b2b_mw() local
151 mmio = ndev->self_mmio; in gen3_setup_b2b_mw()
155 iowrite64(bar_addr, mmio + GEN3_IMBAR1XLMT_OFFSET); in gen3_setup_b2b_mw()
156 bar_addr = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET); in gen3_setup_b2b_mw()
160 iowrite64(bar_addr, mmio + GEN3_IMBAR2XLMT_OFFSET); in gen3_setup_b2b_mw()
161 bar_addr = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET); in gen3_setup_b2b_mw()
165 iowrite64(0, mmio + GEN3_IMBAR1XBASE_OFFSET); in gen3_setup_b2b_mw()
166 iowrite64(0, mmio + GEN3_IMBAR2XBASE_OFFSET); in gen3_setup_b2b_mw()
262 void __iomem *mmio; in ndev_ntb3_debugfs_read() local
269 mmio = ndev->self_mmio; in ndev_ntb3_debugfs_read()
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/linux/drivers/ntb/hw/amd/
H A Dntb_hw_amd.c125 void __iomem *mmio, *peer_mmio; in amd_ntb_mw_set_trans() local
142 mmio = ndev->self_mmio; in amd_ntb_mw_set_trans()
166 write64(base_addr, mmio + limit_reg); in amd_ntb_mw_set_trans()
189 writel(base_addr, mmio + limit_reg); in amd_ntb_mw_set_trans()
355 void __iomem *mmio = ndev->self_mmio; in amd_ntb_link_enable() local
359 writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET); in amd_ntb_link_enable()
371 void __iomem *mmio = ndev->self_mmio; in amd_ntb_link_disable() local
375 writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET); in amd_ntb_link_disable()
432 void __iomem *mmio = ndev->self_mmio; in amd_ntb_db_read() local
434 return (u64)readw(mmio + AMD_DBSTAT_OFFSET); in amd_ntb_db_read()
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/linux/drivers/ssb/
H A Dscan.c177 lo = readw(bus->mmio + offset); in scan_read32()
178 hi = readw(bus->mmio + offset + 2); in scan_read32()
184 return readl(bus->mmio + offset); in scan_read32()
207 iounmap(bus->mmio); in ssb_iounmap()
211 pci_iounmap(bus->host_pci, bus->mmio); in ssb_iounmap()
219 bus->mmio = NULL; in ssb_iounmap()
226 void __iomem *mmio = NULL; in ssb_ioremap() local
233 mmio = ioremap(baseaddr, SSB_CORE_SIZE); in ssb_ioremap()
237 mmio = pci_iomap(bus->host_pci, 0, ~0UL); in ssb_ioremap()
244 mmio = (void __iomem *)baseaddr; in ssb_ioremap()
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