Home
last modified time | relevance | path

Searched refs:mmWD_UTCL1_STATUS (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h305 #define mmWD_UTCL1_STATUS … macro
H A Dgc_9_1_offset.h301 #define mmWD_UTCL1_STATUS … macro
H A Dgc_9_2_1_offset.h295 #define mmWD_UTCL1_STATUS … macro
H A Dgc_10_1_0_offset.h2311 #define mmWD_UTCL1_STATUS … macro
H A Dgc_10_3_0_offset.h2402 #define mmWD_UTCL1_STATUS … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c207 SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
H A Dgfx_v10_0.c337 SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),